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High-Performance dsPIC33A Core with Floating-Point Unit, High Resolution PWM, High-Speed ADCs, CAN FD, I3C, Resolver Interface, Security Features
High-Performance dsPIC33A Core with Floating-Point Unit, High Resolution PWM, High-Speed ADCs, CAN FD, I3C, Resolver Interface, Security Features
  1. Home
  2. 18 Resolver-to-Digital Converter (RDC)
  3. 18.4 Operation
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  • Operating Conditions
  • High-Performance DSP CPU
  • Memory Features
  • Security Features
  • High-Resolution PWM
  • High-Speed Analog-to-Digital Converters
  • Peripheral Features
  • Controller Features
  • Analog Features
  • Safety Features
  • Functional Safety
  • Qualification
  • Programming and Debug Interfaces
  • dsPIC33AK256MPS306 Family Features
  • Pin Diagrams
  • Pinout I/O Descriptions
  • To Our Valued Customers
  • Terminology Cross Reference
  • 1 Device Overview
  • 2 Guidelines for Getting Started with Digital Signal Controllers
  • 3 CPU
  • 4 Memory Organization
  • 5 Data Memory
  • 6 Flash Program Memory
  • 7 Configuration Bits
  • 8 Security Module
  • 9 Resets
  • 10 Interrupt Controller
  • 11 I/O Ports with Edge Detect
  • 12 Oscillator and Clocking Module
  • 13 Direct Memory Access (DMA) Controller
  • 14 CAN Flexible Data-Rate (FD) Protocol Module
  • 15 High-Resolution PWM with Fine-Edge Placement
  • 16 40 MSPS Analog-to-Digital Converter (ADC)
  • 17 Integrated Touch Controller (ITC)
  • 18 Resolver-to-Digital Converter (RDC)
    • 18.1 Introduction
    • 18.2 Architectural Overview
    • 18.3 Register Summary
    • 18.4 Operation
      • 18.4.1 Excitation Signal Generation
      • 18.4.2 Demodulation and CIC Filter
      • 18.4.3 CORDIC Block
    • 18.5 Interrupts
    • 18.6 Application Example
    • 18.7 Power-Saving Modes
  • 19 High-Speed Analog Comparator with Slope Compensation DAC
  • 20 Quadrature Encoder Interface (QEI)
  • 21 Universal Asynchronous Receiver Transmitter (UART)
  • 22 Serial Peripheral Interface (SPI)
  • 23 Inter-Integrated Circuit (I2C)
  • 24 Improved Inter-Integrated Circuit (I3C)
  • 25 Single-Edge Nibble Transmission (SENT)
  • 26 Bidirectional Serial Synchronous (BiSS) Module
  • 27 Timers
  • 28 Capture/Compare/PWM/Timer Modules (SCCP/MCCP)
  • 29 Configurable Logic Cell (CLC)
  • 30 Peripheral Trigger Generator (PTG)
  • 31 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
  • 32 Current Bias Generator (CBG)
  • 33 UREF Reference Output
  • 34 Operational Amplifier (Op Amp)
  • 35 Watchdog Timer (WDT)
  • 36 Deadman Timer (DMT)
  • 37 Device Power-Saving Modes
  • 38 JTAG Interface
  • 39 In-Circuit Debugger
  • 40 Instruction Set Summary
  • 41 Development Support
  • 42 Electrical Characteristics
  • 43 Packaging Information
  • 44 Revision History
  • 45 Product Identification System
  • Microchip Information

18.4 Operation

The RDC module implements signal generation, demodulation, filtering and tracking mechanisms essential for driving a resolver and processing its output signals. This module can be divided into the following sections:
  • Excitation Signal Generation
  • Demodulation and CIC Filter
  • CORDIC Block

DS70005629B

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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