18.2 PPS Inputs

Each digital peripheral has a dedicated PPS Peripheral Input Selection (xxxPPS) register, with which the input pin to the peripheral is selected. Devices that have 20 leads or less (8/14/16/20) allow PPS routing to any I/O pin, while devices with 28 leads or more allow PPS routing to I/Os contained within two ports (see the table below). The outputs of the Signal Routing Port (SRPORT) can also be used as inputs to other peripherals using PPS.

Important: The notation “xxx” in the generic register name is a placeholder for the peripheral identifier. For example, xxx = T0CKI for the T0CKIPPS register.

Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.

Table 18-1. PPS Input Selection Table
PeripheralPPS Input RegisterDefault Pin Selection at PORRegister Reset Value at PORAvailable Input Port
CLBOUTLCLBDEBUG028-Pin Devices40-Pin Devices
External Interrupt INTPPSRB0‘b001 010YesYesAB—AB———
Timer0 ClockT0CKIPPSRA4‘b000 100YesYesAB—AB———
Timer1 ClockT1CKIPPSRC0‘b010 000YesYesA—CA—C——
Timer1 GateT1GPPSRB5‘b001 101YesYes—BC—BC——
Timer3 ClockT3CKIPPSRC0‘b010 000YesYes—BC—BC——
Timer3 GateT3GPPSRC0‘b010 000YesYesA—CA—C——
Timer2 InputT2INPPSRC3‘b010 011YesYesA—CA—C——
Timer4 InputT4INPPSRC5‘b010 101YesYes—BC—BC——
CCP1CCP1PPSRC2‘b010 010YesYes—BC—BC——
CCP2CCP2PPSRC1‘b010 001YesYes—BC—BC——
PWM Input 0PWMIN0PPSRC2‘b010 010YesYes—BC—BC——
PWM Input 1PWMIN1PPSRC1‘b010 001YesYes—BC—BC——
PWM1 External ResetPWMIN1ERSPPSRC3‘b010 011YesYesA—CA—C——
PWM2 External ResetPWMIN2ERSPPSRC5‘b010 101YesYes—BC—BC——
CLCIN0CLCIN0PPSRA0‘b000 000YesYesA—CA—C——
CLCIN1CLCIN1PPSRA1‘b000 001YesYesA—CA—C——
CLCIN2CLCIN2PPSRB6‘b001 110YesYes—BC—B—D—
CLCIN3CLCIN3PPSRB7‘b001 111YesYes—BC—B—D—
SCL1/SCK1SSP1CLKPPS(1)RC3‘b010 011YesYes—BC—BC——
SDA1/SDI1SSP1DATPPS(1)RC4‘b010 100YesYes—BC—BC——
SS1SSP1SSPPSRA5‘b000 101YesYesA—CA——D—
SCL2/SCK2SSP2CLKPPS(1)RB1‘b001 001YesYes—BC—B—C—
SDA2/SDI2SSP2DATPPS(1)RB2‘b001 010YesYes—BC—B—C—
SS2SSP2SSPPSRB0‘b001 000YesYes—BC—B—D—
RX1/DT1RX1PPSRC7‘b010 111YesYes—BC—BC——
CK1CK1PPSRC6‘b010 110YesYes—BC—BC——
RX2/DT2RX2PPSRB7‘b001 111YesYes—BC—B—D—
CK2CK2PPSRB6‘b001 110YesYes—BC—B—D—
ADC Conversion TriggerADACTPPSRB4‘b001 100YesYes—BC—B—D—
CLB ClockCLBCLKPPSRC4‘b001 100YesYesABCABCDE
CLB Input 0CLBIN0PPSRC0‘b001 000YesYesABCABCDE
CLB Input 1CLBIN1PPSRC1‘b001 001YesYesABCABCDE
CLB Input 2CLBIN2PPSRC2‘b001 010YesYesABCABCDE
CLB Input 3CLBIN3PPSRC3‘b001 011YesYesABCABCDE
Note:
  1. Bidirectional pin. The corresponding output must select the same pin.