29 CLB - Configurable Logic Block
The Configurable Logic Block (CLB) is a collection of logic elements that can be programmed to perform a wide variety of digital logic functions. The logic function may be completely combinatorial, sequential, or a combination of the two, enabling users to incorporate hardware-based custom logic into their applications.
- 32 Basic Logic Elements (BLEs):
- Each BLE consists of one 4-input 16-value Look-up Table (LUT), a Flip-Flop, a mux for combinational or registered result, and an AND gate to zero the output when the module is in Reset
- Interconnected Fabric:
- Connects all 32 BLEs
- Dedicated 3-bit hardware counter
- Selectable clock sources with configurable clock divider
- One PPS clock input pin
- Up to four PPS inputs
- Up to eight PPS outputs with read-lock
- CLB Auto Configuration:
- Can be automatically configured during system boot
- Allows for CLB operation without CPU
The CLB module is configured using two sets of register interfaces: the standard Special Function Register (SFR) interface, and the Microchip CLB Synthesizer.
These SFRs allow user software the ability to enable the module, program input bits into the CLB memory, select a clock source, and enable PPS outputs for specific BLE outputs.
The Microchip CLB Synthesizer allows for complete configuration of the CLB module. Configuration data for the CLB is written from Program Memory through the NVM Scanner Module. The Interface does not appear as SFRs in the Register Map and is not directly user-accessible; it is accessible only through a programming system such as Microchip MPLAB® Tools for VS Code® that support programming the CLB.