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PIC16F13256/76 Full-Featured 28/40-Pin Microcontrollers
Introduction
PIC16F13276 Family Summary
Core Features
Memory
Operating Characteristics
Power-Saving Functionality
Digital Peripherals
Analog Peripherals
Clocking Structure
Programming/Debug Features
1 Packages
2 Pin Diagrams
3 Pin Allocation Tables
4 Guidelines for Getting Started with PIC16F13276 Microcontrollers
4.1 Basic Connection Requirements
4.2 Power Supply Pins
4.3 Master Clear (MCLR) Pin
4.4 In-Circuit Serial Programming™ (ICSP™) Pins
4.5 Unused I/Os
5 Register and Bit Naming Conventions
5.1 Register Names
5.2 Bit Names
5.3 Register and Bit Naming Exceptions
6 Register Legend
7 Enhanced Mid-Range CPU
7.1 Automatic Interrupt Context Saving
7.2 16-Level Stack with Overflow and Underflow
7.3 File Select Registers
7.4 Instruction Set
8 Device Configuration
8.1 Configuration Words
8.2 Enhanced Code Protection
8.3 User ID
8.4 Device ID and Revision ID
8.5 Register Definitions: Configuration Settings
8.6 Register Definitions: Device ID and Revision ID
8.7 Register Definitions: Software ICSP Enable
9 Memory Organization
9.1 Program Memory Organization
9.2 Data Memory Organization
9.3 STATUS Register
9.4 PCL and PCLATH
9.5 Stack
9.6 Indirect Addressing
9.7 Register Definitions: Memory Organization
9.8 Register Summary - Memory Organization
10 Resets
10.1 Power-on Reset (POR)
10.2 Brown-out Reset (BOR)
10.3 Low-Power Brown-out Reset (LPBOR)
10.4 MCLR Reset
10.5 Windowed Watchdog Timer (WWDT) Reset
10.6 Watchdog Timer (WDT) Reset
10.7 RESET Instruction
10.8 Stack Overflow/Underflow Reset
10.9 Power-Up Timer (PWRT)
10.10 Start-Up Sequence
10.11 Memory Execution Violation
10.12 Determining the Cause of a Reset
10.13 Power Control (PCONx) Register
10.14 Register Definitions: Power Control
10.15 Register Summary - Power Control
11 OSC - Oscillator Module (With Fail-Safe Clock Monitor)
11.1 Clock Source Types
11.2 Clock Switching
11.3 Fail-Safe Clock Monitor (FSCM)
11.4 Active Clock Tuning (ACT)
11.5 Register Definitions: Oscillator Module
11.6 Register Summary - Oscillator Module
12 INT - Interrupts
12.1 Overview
12.2 INTCON Register
12.3 PIE Registers
12.4 PIR Registers
12.5 Operation
12.6 Interrupt Latency
12.7 Interrupts During Sleep
12.8 INT Pin
12.9 Automatic Context Saving
12.10 Register Definitions: Interrupt Control
12.11 Register Summary - Interrupt Control
13 Power-Saving Modes
13.1 Doze Mode
13.2 Sleep Mode
13.3 Idle Mode
13.4 Peripheral Operation in Power-Saving Modes
13.5 Register Definitions: Power-Savings Control
13.6 Register Summary - Power-Savings Control
14 WWDT - Windowed Watchdog Timer
14.1 Independent Clock Source
14.2 WWDT Operating Modes
14.3 Time-Out Period
14.4 Watchdog Window
14.5 Clearing the Watchdog Timer
14.6 Operation During Sleep
14.7 Register Definitions: Windowed Watchdog Timer Control
14.8 Register Summary - WDT Control
15 NVM - Nonvolatile Memory Control
15.1 Program Flash Memory (PFM)
15.2 Data Flash Memory (DFM)
15.3 Register Definitions: Nonvolatile Memory Control
15.4 Register Summary - NVM Control
16 I/O Ports
16.1 Overview
16.2 PORTx - Data Register
16.3 LATx - Output Latch
16.4 TRISx - Direction Control
16.5 ANSELx - Analog Control
16.6 WPUx - Weak Pull-Up Control
16.7 INLVLx - Input Threshold Control
16.8 SLRCONx - Slew Rate Control
16.9 ODCONx - Open-Drain Control
16.10 Edge Selectable Interrupt-on-Change
16.11 I2C Pad Control
16.12 I/O Priorities
16.13 MCLR/VPP/RE3 Pin
16.14 Register Definitions: Port Control
16.15 Register Summary - I/O Ports
17 IOC - Interrupt-on-Change
17.1 Overview
17.2 Enabling the Module
17.3 Individual Pin Configuration
17.4 Interrupt Flags
17.5 Clearing Interrupt Flags
17.6 Operation in Sleep
17.7 Register Definitions: Interrupt-on-Change Control
17.8 Register Summary - Interrupt-on-Change
18 PPS - Peripheral Pin Selection Module
18.1 Overview
18.2 PPS Inputs
18.3 PPS Outputs
18.4 TRISxyPPS Register
18.5 Bidirectional Pins
18.6 PPS Lock
18.7 Operation During Sleep
18.8 Effects of a Reset
18.9 Register Definitions: Peripheral Pin Select (PPS)
18.10 Register Summary - Peripheral Pin Select Module
19 CRC - Cyclic Redundancy Check Module with Memory Scanner
19.1 Module Overview
19.2 Polynomial Implementation
19.3 Data Sources
19.4 CRC Check Value
19.5 CRC Interrupt
19.6 Configuring the CRC Module
19.7 Scanner Module Overview
19.8 Scanning Modes
19.9 Configuring the Scanner
19.10 Scanner Interrupts
19.11 WWDT Interaction
19.12 Operation During Sleep
19.13 Peripheral Module Disable
19.14 Register Definitions: CRC and Scanner Control
19.15 Register Summary - CRC
20 PMD - Peripheral Module Disable
20.1 Overview
20.2 Disabling a Module
20.3 Enabling a Module
20.4 Register Definitions: Peripheral Module Disable
20.5 Register Summary - PMD
21 CLKREF - Reference Clock Output Module
21.1 Clock Source
21.2 Programmable Clock Divider
21.3 Selectable Duty Cycle
21.4 Operation in Sleep Mode
21.5 Register Definitions: Reference Clock
21.6 Register Summary - Reference CLK
22 TMR0 - Timer0 Module
22.1 Timer0 Operation
22.2 Clock Selection
22.3 Timer0 Output and Interrupt
22.4 Operation During Sleep
22.5 Register Definitions: Timer0 Control
22.6 Register Summary - Timer0
23 TMR1 - Timer1 Module with Gate Control
23.1 Timer1 Operation
23.2 Clock Source Selection
23.3 Timer1 Prescaler
23.4 Secondary Oscillator
23.5 Timer1 Operation in Asynchronous Counter Mode
23.6 Timer1 16-Bit Read/Write Mode
23.7 Timer1 Gate
23.8 Timer1 Interrupt
23.9 Timer1 Operation During Sleep
23.10 CCP Capture/Compare Time Base
23.11 CCP Special Event Trigger
23.12 Peripheral Module Disable
23.13 Register Definitions: Timer1 Control
23.14 Register Summary - Timer1
24 TMR2 - Timer2 Module
24.1 Timer2 Operation
24.2 Timer2 Output
24.3 External Reset Sources
24.4 Timer2 Interrupt
24.5 PSYNC Bit
24.6 CSYNC Bit
24.7 Operating Modes
24.8 Operation Examples
24.9 Timer2 Operation During Sleep
24.10 Register Definitions: Timer2 Control
24.11 Register Summary - Timer2
25 CCP - Capture/Compare/PWM Module
25.1 CCP Module Configuration
25.2 Capture Mode
25.3 Compare Mode
25.4 PWM Overview
25.5 Register Definitions: CCP Control
25.6 Register Summary - CCP Control
26 Capture, Compare, and PWM Timers Selection
26.1 Register Definitions: Capture, Compare, and PWM Timers Selection
26.2 Register Summary - Capture, Compare, and PWM Timers Selection
27 PWM - Pulse-Width Modulator with Compare
27.1 Output Slices
27.2 Period Timer
27.3 Clock Sources
27.4 External Period Resets
27.5 Buffered Period and Parameter Registers
27.6 Synchronizing Multiple PWMs
27.7 Interrupts
27.8 Operation During Sleep
27.9 Register Definitions: PWM Control
27.10 Register Summary - PWM
28 CLC - Configurable Logic Cell
28.1 CLC Setup
28.2 CLC Interrupts
28.3 Effects of a Reset
28.4 Output Mirror Copies
28.5 Operation During Sleep
28.6 CLC Setup Steps
28.7 Register Overlay
28.8 Register Definitions: Configurable Logic Cell
28.9 Register Summary - CLC Control
29 CLB - Configurable Logic Block
29.1 CLB Module Enable
29.2 Basic Logic Element (BLE)
29.3 Dedicated 3-Bit Counter
29.4 CLB Module Inputs
29.5 CLB Module Outputs
29.6 CLB Clock Selection
29.7 CLB Interrupts
29.8 Operation During Sleep Mode
29.9 CLB Configuration
29.10 CLB Debug
29.11 Register Definitions: Configurable Logic Block
29.12 Register Summary - CLB Control
30 MSSP - Host Synchronous Serial Port Module
30.1 SPI Mode Overview
30.2 I2C Mode Overview
30.3 Baud Rate Generator
30.4 Register Definitions: MSSP Control
30.5 Register Summary - MSSP Control
31 EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
31.1 EUSART Asynchronous Mode
31.2 Clock Accuracy with Asynchronous Operation
31.3 EUSART Baud Rate Generator (BRG)
31.4 EUSART Synchronous Mode
31.5 EUSART Operation During Sleep
31.6 Register Definitions: EUSART Control
31.7 Register Summary - EUSART
32 ADC - Analog-to-Digital Converter with Computation Module
32.1 ADC Configuration
32.2 ADC Operation
32.3 ADC Acquisition Requirements
32.4 Computation Operation
32.5 Register Definitions: ADC Control
32.6 Register Summary - ADC
33 DAC - Digital-to-Analog Converter Module
33.1 Output Voltage Selection
33.2 Ratiometric Output Level
33.3 Buffered DAC Output Range Selection
33.4 Operation During Sleep
33.5 Effects of a Reset
33.6 Register Definitions: DAC Control
33.7 Register Summary - DAC
34 CMP - Comparator Module
34.1 Comparator Overview
34.2 Comparator Control
34.3 Comparator Hysteresis
34.4 Comparator Interrupt
34.5 Comparator Positive Input Selection
34.6 Comparator Negative Input Selection
34.7 Comparator Response Time
34.8 Analog Input Connection Considerations
34.9 Operation in Sleep Mode
34.10 ADC Auto-Trigger Source
34.11 Register Definitions: Comparator Control
34.12 Register Summary - Comparator
35 HLVD - High/Low-Voltage Detect
35.1 Operation
35.2 Setup
35.3 Current Consumption
35.4 HLVD Start-Up Time
35.5 Applications
35.6 Operation During Sleep
35.7 Operation During Idle and Doze Modes
35.8 Effects of a Reset
35.9 Register Definitions: HLVD Control
35.10 Register Summary - HLVD
36 FVR - Fixed Voltage Reference
36.1 Independent Gain Amplifiers
36.2 FVR Stabilization Period
36.3 Register Definitions: FVR
36.4 Register Summary - FVR
37 Temperature Indicator Module
37.1 Module Operation
37.2 Temperature Calculation
37.3 ADC Acquisition Time
37.4 Register Definitions: Temperature Indicator
37.5 Register Summary - Temperature Indicator
38 Charge Pump
38.1 Manually Enabled
38.2 Automatically Enabled
38.3 Disabled
38.4 Charge Pump Oscillator
38.5 Charge Pump Threshold
38.6 Charge Pump Ready
38.7 Register Definitions: Charge Pump
38.8 Register Summary - Charge Pump
39 Instruction Set Summary
39.1 Read-Modify-Write Operations
39.2 Standard Instruction Set
40 ICSP™ - In-Circuit Serial Programming™
40.1 High-Voltage Programming Entry Mode
40.2 Low-Voltage Programming Entry Mode
40.3 Common Programming Interfaces
41 Register Summary
42 Electrical Specifications
42.1 Absolute Maximum Ratings
42.2 Standard Operating Conditions
42.3 DC Characteristics
42.4 AC Characteristics
43 DC and AC Characteristics Graphs and Tables
44 Packaging Information
44.1 Package Details
45 Appendix A: Revision History
Product Identification System
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature

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