10.6 Migrating Designs to Libero SoC 2021.2

10.6.1 Design and Core Invalidation

10.6.1.1 RTG4FCCCECALIB Design Invalidation

RTG4FCCCECALIB designs performed with earlier Libero SoC versions will be invalidated when Libero SoC v2021.2 is invoked.

  • Error: RTG4 CCC instances listed below must be updated to RTG4FCCCECALIB core v2.2.005 or later and regenerated. For more information about this requirement, refer to RTG4 Customer Notification CN19009C on the Microchip website.
  • INFO: Converted design '...' to pre-Synthesize state because it contains RTG4 CCC instances that must be updated. Please check the log for more information.
  • INFO: Converted design '...' to pre-Compile state because it contains RTG4 CCC instances that must be updated. Please check the log for more information.

10.6.2 Core Enhancements and Upgrades

The following table lists the core enhancements and upgrades. For more information about updating a core version, see section Updating a Core Version.

Table 10-4. Core Enhancements and Upgrades
Core2021.2 VersionStatusComments
PF_DRI1.1.104ProductionRemoved the PCIe tab in the PF_DRI configurator. For information about how to reconfigure dynamically the PCIe configuration regiseters, see the PolarFire PCIe User Guide.
PF_IO2.0.104ProductionThe interface was corrected when configuring input and output register modes differently.
PF_IOD_GENERIC_RX2.1.104Production
  • Fixed issue when using the option to expose fractional clock parallel data port.
  • Previously, IOD_GENERIC_RX with a fabric ratio of 1 generated false path constraints that did not exist in the design. These constraints have been removed.
  • Exposes eye_width_monitor port with RX_DDRX_B_G_A configuration.
PF_IOD_GENERIC_TX2.0.111ProductionSee section User Control of Output Clock Port Pattern on IOD Generic Transmit Interface.
PF_IOD_TX_CCC1.0.122ProductionRepackaged with latest core version of PF_CCC.
PF_LPDDR32.3.113ProductionSee section LPDDR3 Self-refresh Entry and Exit.
PF_QDR1.8.203ProductionSee section PF_QDR DOFF_N Port and Fast Simulation Enhancements.
PF_RGMII_TO_GMII1.3.103ProductionRepackaged with the latest core versions of PF_IOD_GENERIC_RX and PF_IOD_GENERIC_TX.
RTG4FCCCECALIB2.2.005ProductionSee section CN19009C: Improvements to RTG4 FCCC with Enhanced PLL Calibration Core.
RTG4FDDRC2.0.102ProductionEnables fractional clock frequency.
RTG4FDDRC_INIT2.0.102ProductionEnables fractional clock frequency.
SmartFusion2/IGLOO2 FDDRC2.0.101ProductionEnables fractional clock frequency.

10.6.3 Updating a Core Version

Perform the following procedure to update a core version:
  1. Download the latest version of the core into your vault.
  2. Upgrade each configured core in your design to the latest version by right-clicking on the core component in the design hierarchy and selecting Replace Component Version.
  3. Regenerate the core.
  4. Derive the Timing Constraints again from the Constraint Manager tool to use the latest generated core timing constraints.
  5. Rerun the design flow.