9.4 Software Features and Enhancements

• Created new Vivado HLS to SmartHLS Migration Guide.
• Added device support for IGLOO2. SmartHLS IDE’s device-selection menu now has a drop-down with a complete list of supported devices.

• Improved expression balancing optimization to reduce cycle latency of generated hardware.
• A new branchless flatten function feature improves parallelism by removing branch operations.
• A new replicate ROM pragma enables and controls ROM (array) replication for higher memory bandwidth.

Enhanced SW/HW co-simulation flow to support more sophisticated software test benches.

• Improved support for C++ features: templates, classes, inheritance, namespaces, nested types, and typedef.

• Added support for packed FIFOs (see hls::FIFO Argument) and constant static struct members.

Improved struct support.

• Added a new pack pragma to implement a struct type interface or memory as a wide scalar.
• Added support struct as a return type for the top-level HLS function.

Libero SoC v2021.3 adds the following new features to the SmartDesign tool, enhancing the front-end design entry capability.

• The Flattening Hierarchical SmartDesign option has been added, which allows hierarchical SmartDesign instances to be flattened within a SmartDesign canvas. This option is an indirect undo of Creating a Hierarchical SmartDesign.
• The Memory Map dialog box is now a docking window available as a split view in the SmartDesign canvas similar to the Smart Search and Connect and Synthesis Attributes windows. This enhances the user experience significantly by providing simultaneous access to both the design and the memory map. The memory map can be refreshed from the toolbar if the design has been modified. Also, users can cross probe from the Memory Map window to the SmartDesign canvas.
• Design Rule Checks have been added to identify AMBA bus interface data and ID width mismatches between initiators and targets while generating a SmartDesign component. The AMBA bus interface data and ID width mismatch DRCs are warnings by default. Users can choose to upgrade the DRCs to errors from Libero Project Settings. The option to upgrade or downgrade the Memory Map DRCs is now available as a Libero Project Setting instead of a Libero Preference. Tcl command support has been added for these new project settings.
• Update Component/Instance Version (previously called Replace Component/Instance Version) functionality and dialog user interface have been enhanced, including support for automatic download of the selected core version if needed. The Update Component Version option is now available on instances of core components in a SmartDesign canvas as well. Tcl command support has been added for the same. The option to update the interface(port-list) of a core component's instance in a SmartDesign canvas has been renamed to from Update Component to Update Instance.
• Right-click menu options on SmartDesign canvas objects have been reorganized to now show important functional ones at the top.
• Wildcard support has been added to the Tcl commands for downloading cores, creating core components, and updating core versions.

For more information, see Revision History in the SmartDesign User Guide.

Libero SoC v2021.3 improves the following SmartPower activity annotation capabilities when importing the VCD files.

• Carry chain mapping is now considered when pre-layout VCDs are imported.
• Improved importing of post-synthesis VCD when automatic glitch filtering is off.
• Improved object mapping from system Verilog RTL to post-layout netlist to increase the efficiency of pre-layout VCD import.

For more information on importing VCD files, see the SmartPower User Guide.

Libero SoC v2021.3, FlashPro Express, and SmartDebug detects an out-of-date FlashPro6 programmer. The user can then choose to update the programmer design.

For more information, see section 7.1 in the FlashPro Express User Guide .

The SynplifyPro and Identify tools bundled in Libero SoC v2021.3 have been upgraded to version R-2021.03SP1. Key enhancements are:

• Pipeline register packing into block RAM (LSRAM) for depth-wise split RAM structure is supported for single-port, two-port, and dual-port (PolarFire, PolarFire SoC, RT PolarFire and RTG4)
• RAM reporting enhancement
• Support of MPF050T device
• The Resolve mixed driver option is ON by default
• CDC reporting enhancements for multi-clock RAM

Identify is now fully supported on Ubuntu 18.04. SynplifyPro is supported since R-2021.03M, which was bundled with Libero SoC v2021.2.

For more information, see the Synopsys FPGA Synthesis SynplifyPro ME 2021.03SP1 User Guide.

The ModelSim ME Pro tool bundled in Libero SoC v2021.3 has been upgraded to version 2021.3. There are no new features or fixes specific to Microchip technology in this ModelSim ME Pro version.

Libero SoC v2021.3 includes the following 64-bit executables of Flexera licensing daemons for both Linux and Windows operating systems:

• Linux v11.16.1: actlmgrd, lmgrd, lmhostid, and lmutil
• Windows v11.16.1: actlmgrd.exe, lmgrd.exe, lmhostid.exe, and lmutil.exe.

The licensing daemons can also be downloaded from www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/fpga/licensing.