11.6 Migrating Designs to Libero SoC

11.6.1 Core Enhancements and Upgrades

The following table lists the core enhancements and upgrades.

Table 11-2. Core Enhancements and Upgrades
Core2021.1 VersionStatus

Description

CORERXIODBITALIGN2.2.100ProductionSmartDebug I/O Tap Delays.
PFSOC_INIT_MONITOR1.0.205Pre-productionFixed synthesis error because of floating AND gate.
RTG4_SRAM_AHBL_AXI1.0.117ProductionMade change to not expose Port-B Side of ECC signals when using USRAM option.
SmartFusion2/IGLOO2 TPSRAM1.0.102ProductionAdded support for initializing memory files through TCL.
SmartFusion2/IGLOO2 DPSRAM1.0.102ProductionAdded support for initializing memory files through TCL.
SmartFusion2/IGLOO2 URAM1.0.102ProductionAdded support for initializing memory files through TCL.
PF_RGMII_TO_GMII1.3.102ProductionRepackaged with latest PF_IOD_GENERIC_RX and PF_IOD_GENERIC_TX core versions.
PF_QDR1.8.105Production

PF_QDR: CoreQDR BFM simulation: X observed during read for upper addresses.

PF_INIT_MONITOR2.0.204ProductionFixed synthesis error due to floating AND gate.
PF_IO2.0.102ProductionSeparate register mode for input/output/oe.
PF_IOD_GENERIC_TX2.0.109ProductionThe PF_IOD GUI does not allow non-integer frequencies.
PF_IOD_OCTAL_DDR2.0.102ProductionPF_IOD_OCTAL_DDR configuration issues.
PF_IOD_GENERIC_RX2.1.102ProductionThe PF_IOD GUI does not allow non-integer frequencies.
PF_XCVR (Hidden)2.1.101ProductionIncremental DFE support.
PF_LPDDR32.3.112ProductionAdd a field to the LPDDR3 Configurator GUI to select the PLL Offset value.
PF_DDR42.5.102ProductionDDR4 - QoR - Throughput enhancement (bank group interleaving).
CORESMARTBERT2.8.101Production

No functional change. Repackaged with PF_XCVR v2.1.101.

RN and HB were updated in CoreSmartBERT v2.8.101 compared to CoreSmartBERT v2.8.100.

PF_XCVR_ERM3.1.107ProductionIncremental DFE support.

For more information about updating a core version, see Updating a Core Version.

11.6.2 Updating a Core Version

Perform the following procedure to update a core version:
  1. Download the latest version of the core into your vault.
  2. Upgrade each configured core in your design to the latest version by right-clicking on the core component in the design hierarchy and selecting Replace Component Version.
  3. Regenerate the core.
  4. Derive the Timing Constraints again from the Constraint Manager tool to use the latest generated core timing constraints.
  5. Rerun the design flow.