7.6 Migrating Designs to Libero SoC

7.6.1 Core Enhancements and Upgrades

The following table lists core enhancements and upgrades in Libero SoC v2022.2. For more information about updating a core version, see section Updating a Core Version.

Table 7-9. Core Enhancements and Upgrades
Core2022.2 VersionStatusComments
CORESMARTBERT2.9.102ProductionFor information, see section Enhanced SmartBERT Core for 10 Gbps Protocols.
PF_CCC2.2.214ProductionFor information, see section PLL Phase Alignment when Using Post-Divider or External Feedback Mode.
PF_CRYPTO1.0.110ProductionConfirmed that in PolarFire SoC designs, DRC checks for PCIe and Crypto configurator when clock frequencies are between 70 and 125 MHz.
PF_DDR32.4.119ProductionIntegrated a new CCC core.
PF_DDR42.5.108ProductionIntegrated a new CCC core.
PF_INIT_MONITOR2.0.304ProductionImproved the synchronizer circuit of the output latches.
PF_IOD_CDR_CCC2.1.108ProductionIntegrated new CCC core.
PF_IOD_TX_CCC1.0.125ProductionIntegrated new CCC core.
PF_IOD_GENERIC_RX2.1.109ProductionBecause the same port name cannot be added as input or output to symbol view, the RX_CLK_G_IN port now appears in symbol view if RX_CLK_G is used as an input port.
PF_IOD_OCTAL_DDR2.0.105ProductionIntegrated new CCC core.
PF_LPDDR32.3.117ProductionIntegrated new CCC core.
PF_QDR1.9.101ProductionFor PolarFire, a COREQDR_PF reset now propagates to IODs.
PF_RGMII_TO_GMII1.3.106ProductionIntegrated new CCC core.
PF_TAMPER1.0.209ProductionFor information, see section PF_TAMPER Enhancement to Latch Outputs when Using System Controller Suspend Mode.
PF_SPACEWIRE_RX_PHY1.0.107ProductionFor information, see section RT PolarFire SpaceWire RX PHY Core.
PFSOC_INIT_MONITOR1.0.304ProductionSame improvements described in PF_INIT_MONITOR above.
RTG4FCCC2.0.204ProductionFor information, see section Changing Default Behavior of GLx_Yx_ARST_N Signals in the CCC Configurator.
RTG4FCCCECALIB2.2.007ProductionFor information, see sections Changing Default Behavior of GLx_Yx_ARST_N Signals in the CCC Configurator and Added Simulation Support for RTG4 PLL Feedback Delay.

7.6.2 Updating a Core Version

Perform the following procedure to update a core version:
  1. Download the latest version of the core into your vault.
  2. Upgrade each configured core in your design to the latest version by right-clicking on the core component in the design hierarchy and selecting Update Component Version. The component is regenerated automatically.
    Important: The Update Component Version option is now available on instances of core components in a SmartDesign canvas as well. In addition, the selected core version is downloaded automatically from the Update Component Version dialog itself if needed.
  3. Review the SmartDesign components and user RTL files in which the core component has been instantiated. If the port-list of the core component is modified after updating to the new core version, right click the core component's instance in the SmartDesign and select Update Instance to update its port-list. Check for any pin/port disconnections in the SmartDesign or for any new pins exposed on the core component's instance, and then connect them or tie them off as needed and regenerate the SmartDesign component.
  4. Build Design Hierarchy and Derive the Timing Constraints again from the Constraint Manager tool to use the latest generated core timing constraints.
  5. Rerun the design flow.