8.7 Resolved Issues

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The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2022.1 that have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 8-2. Customer-reported Defects and Enhancement Requests with Case Numbers
Case Number	Summary	Resolution
00770055	PLL configuration with External Feedback generates errors during Place and Route.	Configurator-generated constraints are fixed to not add `-pll_feedback` and `-pll_output` when feedback source is `Dedicate Pad`.
00758973,00783075	FCCC auto-derived constraints produce errors during compile.	An issue with path search between the PLL output and PLL feedback has been fixed.
00771288, 00909815	KIT_LICENSE_IP: Device Family parameter/configurator issue with MPF300T devices with Gold license.	The device mapping information is now passed correctly to COREFIFO when a Gold license is used.
00780224	When the FDDR/MDDR is configured to support 4GB, it cannot access the entire 32-bit AXI address range. Designs that do not map the MSB of the 32-bit AXI address to the DDR memory address are not affected (that is, if the AXI address does not exceed a 2GB address space).	For more information, see section DDR Memory Controller Change of Memory Density .
00805467	New line character is not seen as a separator between two SDC commands in the SDC file.	Interpretation of commands between curly braces in SDC files has been fixed.
00815661	DRC violations message in SSN Analyzer.	For DRC violations, DRC warning messages will be shown to the noise margin and excluded IO page.
00813594	Enhancement request on Libero support for RHEL 7.9.	Starting with v2022.1, Libero SoC will be supported on RHEL/CentOS 7.9.
00827297	Library logical name WORK not treated as current working library by Synplify Pro.	Synplify Pro S-2021.09M adds a new option to treat the VHDL library logical name “work” as the current library. `set_option -work_is_curlib 1`
00843870	Synthesis error on inferred RAM.	When Synplify Pro promoted a GND net to global, Libero failed "per DRC, static values are expected to be assigned to this pin." Now Synplify Pro will not promote the GND pin to Global.
00845159,00803696	Synthesis error occurs when trying to open encrypted HDL files on 11th generation processor machines.	Encrypted designs are supported and will pass successfully with Synplify Pro S2021.09M on 11th generation processor machines.
00847579	Error message with a specific clock signal during Multipass Place and Route.	`Compare failed` error message was reported in the iteration summary report because the Frequency field was removed from timing reports. Multipass Place and Route now evaluates the best seed by Worst Slack.
00849469	PF_SOC: MSS: QSPI I/Os do not support 1.8V.	Updated DRC for all peripherals.
00850843	SmartDebug enhancement request: Export embedded non-volatile memory (eNVM) and secure non-volatile memory (sNVM) to file.	For more information, see section SmartDebug Option to Export Contents of eNVM and sNVM.
00852603	SmartTime reports unreasonably high clock generation time.	Fixed an issue when calculating the short path for some gated clock designs.
00853926	Signal integrity settings from I/O Editor have no effect on design implementation.	This issue affected the I/O settings of lanes and `REFCLK` of transceivers when replication was enabled in Place and Route. Rerun Place and Route in Libero SoC v2022.1.
00859317	PF_PCIE issue with PCIE0 BAR0.	Fixed settings when `BAR0` is enabled for the PCIe0 controller, but disabled for the PCIe1 controller.
00859778, 00853856, 00780930	Identify Debugger crashes on 11th generation processor machines.	Identify Debugger invokes successfully to communicate with the board.
00865046	Synthesis error in the customer design.	Synthesis error related to `Not enough net bundle` has been fixed.
00877502, 00877508	PF_PCIE: PolarFire PCIe1 Slot clock and ASPM L1 configuration settings are not updated as per the PCIe GUI configuration	Updated register settings.
00883697	PCIe model does not drive to Elec-Idle ('z')	IGLOO2, SmartFusion2, and RTG4 simulation has been enhanced to support tri-state 'z' behavior on PCIe Tx lines. Using the `vsim` command, users can choose PCIe block to drive between a common voltage signal (typically '0' by default) and Tri state ('z').
00896689	For RTG4 devices, the Program and Connectivity Tool crashes due to the missing library `libpng12-0:i386`.	This library is present after installing Libero 2022.1.
00888205	Remove the empty configuration file generated by configurator	Empty configuration file is no longer generated
00897728	SynplifyPro incorrectly modeling Global.	Clock buffer delays have been updated in Synplify Pro S2021.09M.
00900308	PF_CCC: PolarFire CCC GUI configuration difference between 2021.2 and 2021.3	Fixed issue with output frequency computation.
00913713	KIT_LICENSE_IP: COREFIFO ECC flags not available in Smart Design with Gold license.	The device mapping information is now passed correctly to `COREFIFO` when a Gold license is used.
00925061	Libero batch mode crashes when Internet access is disabled.	When the Internet preferences are disabled, a message is not issued via a dialog box in batch mode.
00967427	For SmartFusion2 and IGLOO2 Libero designs, if the customer selected an eNVM component only in bitstream along with the sanitize all eNVM pages option, the output of Generate Bitstream, Export Bitstream, and Export FlashPro Express Job produces incorrect bitstream file where running ERASE action will program eNVM instead of sanitizing eNVM.	This issue is fixed in Libero v2022.2.
493642-2812294750	Synplify support for nested interfaces.	Removed reference to VHDL nested interface from the Synplify Pro User Guide. It is not supported by Synplify Pro.
493642-2816309250	SmartPower does not support `VDDAUX` set to 3.3v in PolarFire.	Added 2.5v and 3.3v selection for VDDAUX rail in Verify power right click options.
493642-2826151737	Exporting SmartTime User SETs.	For more information, see section SmartTime – User SET.
493642-2833553813	SmartDesign BIF port name change issue.	For more information, see section SmartDesign Enhancements.
493642-2847447625	PF_PCIE: Incorrect use model for `PERSTn` when RootPort.	For more information, see section PCIe Root-port Capability to Work with APB Initiator to Control the PERSTn Output to Downstream PCIe Endpoints.
493642-2892634270	IGLOO2 CCC external feedback, Place and Route error messages.	Regenerating constraints from the CCC Configurator will not add `-pll_feedback` and `-pll_output` when feedback source is Dedicate Pad. Place and Route will not encounter `No path found` messages.

The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2022.1 that do not have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 8-3. Customer-reported Defects and Enhancement Requests (No Case Numbers)
Summary	Resolution
Problem to close Timing on MPF500 Design, very long PnR Times.	The issue is no longer observed in the current release.
PF_SYSTEM_SERVICES: Simulations fail for system services when they look for sNVM.mem in Linux.	PF_SYSTEM_SERVICES simulation model was updated to work in the Linux environment when sNVM contents are passed.
In the PolarFire DDR4 Configurator, you can enable both ECC and DM at the same time. These should be mutually exclusive selections.	Added a DRC so that the ECC and DM are mutually exclusive.
FlashPro Express fails to perform any programming action using FlashPro 6 using the SPI Target interface. The JTAG interface is not affected.	Fixed an issue during programmer update where the programmer was not closed properly causing subsequent operations to fail.
RTG4: Assertion Failed in /po_nwkiutil.cxx, line 7732 during Place and Route.	An instance of the RGRESET macro routes a triplicated fabric signal to a row global buffer to create a local reset. The three input bits must be driven by three separate logic cones replicating the paths from the source registers.
Output Delay constraint causes IOFF4 error.	The automatic I/O register combining will check whether a timing constrained path already contains a I/O register inserted by Compile, and avoid combining such I/O or registers in the process.
Support PolarFire MPF300 ES Kit based devices with Silver license.	For more information, see section MPF300TS_ES Device Licenses.
PF_XCVR: PF_TXPLL: Update TXPLL Spread Spectrum Clock Generation (SSCG) user interface.	Renamed labels in the Spread Spectrum tab of the TXPLL and CCC configurators as follows: Spread Mode is now Modulation Direction. Spread/Divval is now Modulation Amplitude.
Synthesis warning message from RTG4 FCCC.	Warning message is no longer observed in the synthesis report.
Crash: Signal 011 error in `m_generic.exe`. `ID:map202103act/060/m_generic.exe`	The SynplifyPro crash related to DSP mapping is been fixed.
Erase FABRIC digest when erasing Fabric in ERASE action.	Updated ERASE action to also erase Fabric digest when erasing Fabric.
USB I/Os not supported 1.8V/2.5V.	Added 2.5V and 1.8V as supported voltages for USB in the MSS configurator.
MMUART I/Os not supported 1.2V/1.5V/18V/3.3V.	Updated DRC for I/O voltage supported for peripherals.
PF_CCC: Clock Uncertainty: Inclusion of jitter in CCC/PLL auto-constraint generation.	For more information, see section New Timing Constraint Flow to Automatically Account for Global Clock Jitter.