5.7 Resolved Issues

(Ask a Question)

The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2023.1 that have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 5-3. Customer-reported Defects and Enhancement Requests with Case Numbers
Case Number	Summary	Resolution
1049756	PF_DDR3: Libero crashes with Segfault after DDR3 configurator is used.	The issue has been resolved for all cores that have presets.
1153044	Gated-clocks: unexplainable results shown in the Constraint Coverage Reports (Verify Timing and P&R).	Differential I/O is recognized when no clock constraint is set and is no longer reported as a gated clock.
782145	The `Clock_uncertainty` constraint does not affect Clock Summary frequency calculations.	Added the following message for single corner and max delay: `Clock frequency estimation doesn't account for clock jitter nor clock uncertainty.`
1057942	The SSN Analyzer tool does not sort pins properly.	The SSN Analyzer tool now sorts pins according to their IO pair numbers within each IO bank instead of die pad.
903073	Verify timing reports numerous `Feedback delay set to 0` errors.	See section New set_external_delay SDC Timing Constraint to Specify External Feedback to PLL.
910290	The set_clock_to_output constraint STA behaves incorrectly.	Fixed clock to out constraints when the clock is a generated clock.
1152868	SmartTime v2022.3 does not report Register-Register path in Min-Delay Analysis.	Min-Delay timing analysis is now reported correctly for designs with user sets.
1108176	PF_INIT_MONITOR 2.0.304 default delay values generate warnings in simulation.	The core has been updated with default values to avoid simulation warnings.
900308	FRAC_EN setting for PolarFire CCC in Libero SoC v2022.2.	Changed the Integer Mode tool tip.
1112195	FIC simulation: BFM fails to start.	This issue has been resolved.
1088829	P&R in Libero SoC v2022.2 takes longer than it did with Libero SoC v12.6 and v2021.3.	The success rate for timing closure is now similar.
1141399	I/O Bank assigner fails.	Applied more effective constraints to resolve assignment problems with globals.
1205002	Place and Route fails with no errors generated.	Enhanced path constraints analysis.
01013206, 01019574, 01155308	SmartFusion 2 and IGLOO 2 hardware times-out with stpl file.	JTAG RESET is now the first operation performed, which cleans the JTAG machine state before programming begins.
867146	Allow debug with mixed chain with ProASIC3 devices.	See section Programming and Debug Support for JTAG Chains Containing ProASIC3, IGLOO, SmartFusion, and non-Microchip Devices.
1106405	Exporting SmartDebug data for RTG4 designs on PCs running the Ubuntu operating system causes Libero to crash.	This issue has been resolved.
1157957	SmartDebug cannot write to memory blocks in CoreEDAC using Debug memory in RTG4 designs.	This issue has been resolved.
1080387	PF_XCVR: The RX PLL Simulation model does not recover the clock when RX PLL divider values were set to 322 MHz.	This issue has been resolved.
1204778	PF_INIT_MONITOR: Post-Place and Route simulation 'x' propagation.	The core has been updated with default values to avoid simulation warnings.
1016130	IBIS models for shield signals.	Instances of shield signals have been removed from exported ibis files.
1091699	RTG4: Synthesis support for a register’s known initialization state.	See section New Synplify Version.
ASKFPGA-2025	PolarFire SoC: Die migration fails.	This issue has been resolved. In addition, the Eval packages, if applicable, are shown in the list.
1122306	Importing PDC file from Chip Planner results in a PDC-15 error.	Instances added by min-delay repair are no longer exported because those instances do not exist in the pre-layout netlist.
1072956	HDL_LANGUAGE: HDL checker fails with legitimate system Verilog with include file.	Resolved by registering the files as System Verilog and ignoring sort-1001 messages.
493642-2750566855	PF_CCC: CCC in cascading mode fails in post layout simulation	This issue has been resolved.
1132114	MPF050T, MPFS160T - Error: Cannot find hardwired track `ICB_BANKCLK_bclk_ccw_out_LANECTRL_bclk`.	This issue has been resolved.
—	MPFS250 MIL has been moved to production, but the timing reports says `Preliminary`.	This issue has been resolved.
—	MPFS095T - Error: Cannot find hardwired track `PLL_OUT<0>_iopad_OIN_P`.	This issue has been resolved.
—	For designs containing imported blocks, the Export Netlist fails.	This issue has been resolved.

The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2023.1 that do not have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 5-4. Customer-reported Defects and Enhancement Requests (No Case Numbers)
Summary	Resolution
Incorrect description in Security Policy Manager Debug Policy.	The option is to disable debug access through JTAG (1149.1). Both UI option label and security summary are fixed to omit references to using FlashLock/UPK1.
Post-Route Probe Insertion does not support chain of devices	See section Programming and Debug Support for JTAG Chains Containing ProASIC3, IGLOO, SmartFusion, and non-Microchip Devices.
PolarFire: Incremental Place and Route should report whether placement and routing were preserved.	The following message indicates whether the original placement and routing were preserved after executing incremental Place and Route: `> Routed 0 net(s) incrementally.`
PF_XCVR: SerDes Configuration for lane alignment at startup.	See section TX_PLL: Enable Tx Lane Alignment.
Multicycle constraint is ignored in STA.	Keep track of pins that are renamed when a register is placed in an RTG4 I/O register.
Constraint mapping issue with Enhanced CCC (`output_delay`).	Resolved an issue with clock names when constraints are applied to the post-layout implementation.
RTG4 CCC external feedback delay calculation discrepancy.	See section New set_external_delay SDC Timing Constraint to Specify External Feedback to PLL.
GUI editor for `set_external_delay` constraint.	See section New set_external_delay SDC Timing Constraint to Specify External Feedback to PLL.
Power estimator reports incorrect power consumption.	Thermal Power calculations have been updated in the power estimator.
PF_CCC: Post layout sim shows Lock of PLL always toggles instead of remaining HIGH.	Updated the back-annotated SDF file.
If there is no MSS or a MiV processor in a SmartDesign, exporting an interrupt map report causes Libero to crash.	This issue has been resolved.
In Project Settings > Design Flow, Libero 2022.3 users who check Enable FPGA Hardware Breakpoint Auto Instantiation and then hover over the i near the GUI option should ignore the following message that appears beside the FHB check mark because the new FHB compile implementation allows the FHB to be instantiated on any `CLKINT`s:`FHB will be instantiated only if the fabric logic is driven by a gated clock output of an FCCC`.	This issue has been resolved.
To invoke FHB auto-instantiation flows with PolarFire and PolarFire SoC, you must create your own NDC file using `auto_instantiate_fhb` commands. If the NDC file is named with the postfix `fhb_auto_generated.ndc`, the flow deletes the file and crashes.	This issue has been resolved.
A new FHB implementation allows FHBs to be added to any `CLKINT`/`RCLKINT`/`GCLKINT`/`RGCLKINT` of a design. However, there are some limitations about the kind of topologies allowed. With SmartBERT, the `RCLKINT`s connected to output `RX_CLK_R` and `TX_CLK_R` are considered illegal instances for FHB instantiation. These instances are considered to be illegal because FHB instantiations create an additional `CLKINT` and connect it to the same driver as the `RCLKINT`; however, the `RX_CLK_R` and `TX_CLK_R` nets are considered dedicated lines and allow only one connection. As a result, the additional `CLKINT` cannot make the connection and causes the flows to error-out.	The transceiver-generated clocks `TX_CLK_R` and `RX_CLK_R` cannot be controlled by FHB. Proper DRC messages will be printed if users add these clocks in their NDC files.
Core version of 160 MHz oscillator generates the clock name `OSC_0`/`OSC1_0/I_OSC_160`/`CLK` in derived constraints, but FHB SDC constraints are not applied correctly.	There is no need to modify the oscillator clock name in the derived constraint file when using FHB.
The violation report shows violations (red cross), but the timing report does not (green check). In this case, there is indeed a timing violation and the red cross is correct.	This issue has been resolved.