1.4.1 PolarFire, PolarFire SoC, RT PolarFire, and RT PolarFire SoC

1.4.1.1 Simulation Model Enhancements

The Libero SoC v2025.2 release has the following updates and enhancements to PolarFire Simulation models:

  • Added post-layout back-annotated simulation support for Differential input I/O.
  • Added simulation support for wide-mode programmable input delay taps in PF_IO and PF_IOD_GENERIC_RX cores.

1.4.1.2 IOD Octal DDR Enhancements

Libero SoC v2025.2 introduces several enhancements to improve configurability, timing, and simulation accuracy for IOD Octal DDR:

  • PLL_POWERDOWN_N is now exposed by default to facilitate enabling of the PLL only when the REF_CLK input is stable.
  • Added DQS_DELAY_TAP options up to 139 for expanded tuning flexibility.
  • Any tap value in the full range of 1–255 allowed for the DQS delay setting.
  • Added support for non-integer clock frequency entry to accommodate a wider range of design requirements.
  • Improved timing constraints generation to ensure better coverage and timing robustness.
  • Improved performance by inserting two-stage pipeline and register duplication for Async-assert, Sync-deassert Reset.

1.4.1.3 IOD RX Updates

The Libero SoC v2025.2 release enables Expose fractional clock parallel data in the Fractional Dynamic mode.

1.4.1.4 Added Failsafe ODT_EN Support for SPACEWIRE_RX

Libero SoC v2025.2 adds the option to expose the Failsafe ODT_EN port for the SPACEWIRE_RX core interface.

1.4.1.5 Added DLL Register in the Design Initialization Report

The Libero SoC v2025.2 release adds DLL register details in the Design Initialization report.

1.4.1.6 Added Support for Initial Static Delay on Dynamically Tuned I/O Interfaces

Libero SoC v2025.2 allows IN_DELAY and OUT_DELAY options in PDC and I/O Editor for Dynamic I/O interfaces (except DDR, LPDDR, QDR, CDR) to set the initial startup delay value, which can be dynamically tuned during operation.

1.4.1.7 Enhanced PF_SRAM_AHBL_AXI with High-Reliability Options

Libero SoC v2025.2 adds new options for high reliability to enable fault tolerance logic, synchronous reset, and timeout counts for read and write operations on the AHBL or AXI interface.

1.4.1.8 Enabled Fault Tolerance for PF_SYSTEM_SERVICES

The Libero SoC v2025.2 release adds new options for high reliability to enable fault tolerance logic in the PF_SYSTEM_SERVICES core.

1.4.1.9 CoreAXI4Interconnect and CoreAHB-Lite Cores

Libero SoC v2025.2 refreshes the Memory Map definitions with the new initiator and target terminologies for CoreAXI4Interconnect and CoreAHB-Lite cores.

1.4.1.10 Expanded Live Probe Trigger Controls in SmartDebug

Libero SoC v2025.2 adds support for selecting trigger signal’s edge in SmartDebug when a signal is assigned to Live Probe that acts as a trigger.

1.4.1.11 Upgraded Silver License to Add Support for MPF200T-FCG784

The Libero SoC 2025.2 release upgrades the Silver license for MPF200T device (FCG784 package), with extended device range enabled.