3.4 SPI0PER Filtering Capacitor

In some development use cases, it is necessary to interface to an external board. In that case, the performance of the interface can be improved by adding a small filtering capacitor to the SPI0PER chip select line. The figure below shows the empirical test results and highlights the SPI0PER trace to the BMC connector.

100 nF was added to ground on the CS line (GPIO250/SPI0PER_nCS) using a VIA pad, which is closer to the Glacier ASIC. With this, SPT works reliably up to 30 MHz and the drive strength was tested with max 16 mA.

Figure 3-10. Cap Test Results and Highlighted Trace

The placement of the cap in the schematics is shown below. Cap C51 was added between the GPIO250/SPI0PER_nCS line and GND.

Figure 3-11. Schematic Indicating the Installation of Cap

The best location for C51 is on the back side of the board, underneath the CEC, as shown below. This picture is of the back of the previous development board. The location on the latest evaluation board is similar.

Figure 3-12. Relative Location of the Filtering Cap

The design tools show a detailed view of the required modification in the figure below. This is the database for the latest evaluation board. The yellow trace represents the addition of solder and/or wire needed to complete the modification.

Note: The lead of the resistor is soldered directly to a via pad. The other lead of the resistor is attached to ground via a short piece of wire.

Figure 3-13. Layout View of the Filtering Cap Modification