3 Features

The following are the features of the Axcelerator devices:

• Single-Chip, Nonvolatile Solution
• Up to 100% Resource Utilization with 100% Pin Locking
• 1.5V Core Voltage for Low Power
• Footprint Compatible Packaging
• Flexible, Multi-Standard I/Os:
  • 1.5V, 1.8V, 2.5V, 3.3V mixed voltage operation
  • Bank-selectable I/Os—8 banks per chip
  • Single-ended I/O standards: LVTTL, LVCMOS, 3.3V PCI, and 3.3V PCI-X
  • Differential I/O standards: LVPECL and LVDS
  • Voltage-referenced I/O standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, and SSTL3 Class 1 and 2
  • Registered I/Os
  • Hot-swap compliant I/Os (except PCI)
  • Programmable slew rate and drive strength on outputs
  • Programmable delay and weak pull-up/pull-down circuits on inputs
• Embedded Memory:
  • Variable-aspect 4,608-bit RAM blocks (x1, x2, x4, x9, x18, and x36 organizations available)
  • Independent, width-configurable read and write ports
  • Programmable embedded FIFO control logic
• Segmentable Clock Resources
• Embedded Phase-Locked Loop:
  • 14–200 MHz input range
  • Frequency synthesis capabilities up to 1 GHz
• Deterministic and User-Controllable Timing
• Unique In-System Diagnostic and Debug Capability with Microchip Silicon Explorer II
• Boundary-Scan Testing Compliant with IEEE Standard 1149.1 (JTAG)
• FuseLock™ Programming Technology Protects Against Reverse Engineering and Design Theft

The following table shows the Axcelerator family product profile.