2.4.2 HSTL Class I

High-Speed Transceiver Logic (HSTL) is a general purpose high-speed 1.5V bus standard (EIA/JESD8-6). The Axcelerator devices support Class I. This requires a differential amplifier input buffer and a push-pull output buffer.

The following table lists the DC input and output levels of HSTL Class I.

Table 2-45. DC Input and Output Levels
VIL		VIH		VOL	VOH	IOL	IOH
Min. V	Max. V	Min. V	Max. V	Max. V	Min. V	mA	mA
–0.3	VREF – 0.1	VREF + 0.1	3.6	0.4	VCC – 0.4	8	–8

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