2.8.2 Routed Clocks

The Routed Clock (CLK) is a low-skew network that can drive the clock inputs of all sequential modules in the device (logically equivalent to the HCLK), but has the added flexibility in that it can drive the S0 (Enable), S1, PSET, and CLR input of a register (R-cells and I/O registers) as well as any of the inputs of any C-cell in the device. This allows CLKs to be used not only as clocks, but also for other global signals or high fanout nets. All four CLKs are available everywhere on the chip.

Timing Characteristics

The following tables lists the routed array clock networks of Axcelerator devices.

Table 2-79. AX125 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
Routed Array Clock Networks
t_RCKL	Input low to high	—	3.08	—	3.50	—	4.12	ns
t_RCKH	Input high to low	—	3.13	—	3.56	—	4.19	ns
t_RPWH	Minimum pulse width high	0.57	—	0.64	—	0.75	—	ns
t_RPWL	Minimum pulse width low	0.52	—	0.59	—	0.69	—	ns
t_RCKSW	Maximum skew	—	0.35	—	0.39	—	0.46	ns
t_RP	Minimum period	1.15	—	1.31	—	1.54	—	ns
t_RMAX	Maximum frequency	—	870	—	763	—	649	MHz

Table 2-80. AX250 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J = 70°C
Parameter	Description	–2 Speed		–1 Speed		Std Speed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
Routed Array Clock Networks
t_RCKL	Input low to high	—	2.52	—	2.87	—	3.37	ns
t_RCKH	Input high to low	—	2.59	—	2.95	—	3.47	ns
t_RPWH	Minimum pulse width high	0.57	—	0.64	—	0.75	—	ns
t_RPWL	Minimum pulse width low	0.52	—	0.59	—	0.69	—	ns
t_RCKSW	Maximum skew	—	0.35	—	0.39	—	0.46	ns
t_RP	Minimum period	1.15	—	1.31	—	1.54	—	ns
t_RMAX	Maximum frequency	—	870	—	763	—	649	MHz

Table 2-81. AX500 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
Routed Array Clock Networks
t_RCKL	Input low to high	—	2.31	—	2.63	—	3.09	ns
t_RCKH	Input high to low	—	2.44	—	2.78	—	3.27	ns
t_RPWH	Minimum pulse width high	0.57	—	0.64	—	0.75	—	ns
t_RPWL	Minimum pulse width low	0.52	—	0.59	—	0.69	—	ns
t_RCKSW	Maximum skew	—	0.35	—	0.39	—	0.46	ns
t_RP	Minimum period	1.15	—	1.31	—	1.54	—	ns
t_RMAX	Maximum frequency	—	870	—	763	—	649	MHz

Table 2-82. AX1000 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
Routed Array Clock Networks
t_RCKL	Input low to high	—	3.08	—	3.50	—	4.12	ns
t_RCKH	Input high to low	—	3.13	—	3.56	—	4.19	ns
t_RPWH	Minimum pulse width high	0.57	—	0.64	—	0.75	—	ns
t_RPWL	Minimum pulse width low	0.52	—	0.59	—	0.69	—	ns
t_RCKSW	Maximum skew	—	0.35	—	0.39	—	0.46	ns
t_RP	Minimum period	1.15	—	1.31	—	1.54	—	ns
t_RMAX	Maximum frequency	—	870	—	763	—	649	MHz

Table 2-83. AX2000 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
Routed Array Clock Networks
t_RCKL	Input low to high	—	3.08	—	3.50	—	4.12	ns
t_RCKH	Input high to low	—	3.13	—	3.56	—	4.19	ns
t_RPWH	Minimum pulse width high	0.57	—	0.64	—	0.75	—	ns
t_RPWL	Minimum pulse width low	0.52	—	0.59	—	0.69	—	ns
t_RCKSW	Maximum skew	—	0.35	—	0.39	—	0.46	ns
t_RP	Minimum period	1.15	—	1.31	—	1.54	—	ns
t_RMAX	Maximum frequency	—	870	—	763	—	649	MHz