2.10.4.1 Timing Characteristics

The following figure shows the timing model of SRAM.

Figure 2-59. SRAM Model

The following figures shows the timing waveforms of RAM write and RAM read.

Figure 2-60. RAM Write Timing Waveforms

Figure 2-61. RAM Read Timing Waveforms

The following tables list the timing characteristics of different RAM blocks.

Table 2-93. One RAM Block Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
Write Mode
t_WDASU	Write data setup vs. WCLK	—	1.08	—	1.23	—	1.45	ns
t_WDAHD	Write data hold vs. WCLK	—	0.22	—	0.25	—	0.30	ns
t_WADSU	Write address setup vs. WCLK	—	1.08	—	1.23	—	1.45	ns
t_WADHD	Write address hold vs. WCLK	—	0.00	—	0.00	—	0.00	ns
t_WENSU	Write enable setup vs. WCLK	—	1.08	—	1.23	—	1.45	ns
t_WENHD	Write enable hold vs. WCLK	—	0.22	—	0.25	—	0.30	ns
t_WCKH	WCLK minimum high pulse width	0.75	—	0.75	—	0.75	—	ns
t_WCLK	WCLK minimum low pulse width	0.88	—	0.88	—	0.88	—	ns
t_WCKP	WCLK minimum period	1.63	—	1.63	—	1.63	—	ns
Read Mode
t_RADSU	Read address setup vs. RCLK	—	0.81	—	0.92	—	1.08	ns
t_RADHD	Read address hold vs. RCLK	—	0.00	—	0.00	—	0.00	ns
t_RENSU	Read enable setup vs. RCLK	—	0.81	—	0.92	—	1.08	ns
t_RENHD	Read enable hold vs. RCLK	—	0.00	—	0.00	—	0.00	ns
t_RCK2RD1	RCLK-to-OUT (Pipelined)	—	1.32	—	1.51	—	1.77	ns
t_RCK2RD2	RCLK-to-OUT (Non-Pipelined)	—	2.16	—	2.46	—	2.90	ns
t_RCLKH	RCLK minimum high pulse width	0.77	—	0.77	—	0.77	—	ns
t_RCLKL	RCLK minimum low pulse width	0.93	—	0.93	—	0.93	—	ns
t_RCKP	RCLK minimum period	1.70	—	1.70	—	1.70	—	ns

Note: Timing data for this single block RAM has a depth of 4,096. For all other combinations, use Microchip’s timing software.

Table 2-94. Two RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
Write Mode
t_WDASU	Write data setup vs. WCLK	—	1.39	—	1.59	—	1.87	ns
t_WDAHD	Write data hold vs. WCLK	—	0.00	—	0.00	—	0.00	ns
t_WADSU	Write address setup vs. WCLK	—	1.39	—	1.59	—	1.87	ns
t_WADHD	Write address hold vs. WCLK	—	0.00	—	0.00	—	0.00	ns
t_WENSU	Write enable setup vs. WCLK	—	1.39	—	1.59	—	1.87	ns
t_WENHD	Write enable hold vs. WCLK	—	0.00	—	0.00	—	0.00	ns
t_WCKH	WCLK minimum high pulse width	0.75	—	0.75	—	0.75	—	ns
t_WCLK	WCLK minimum low pulse width	1.76	—	1.76	—	1.76	—	ns
t_WCKP	WCLK minimum period	2.51	—	2.51	—	2.51	—	ns
Read Mode
t_RADSU	Read address setup vs. RCLK	—	1.71	—	1.94	—	2.28	ns
t_RADHD	Read address hold vs. RCLK	—	0.00	—	0.00	—	0.00	ns
t_RENSU	Read enable setup vs. RCLK	—	1.71	—	1.94	—	2.28	ns
t_RENHD	Read enable hold vs. RCLK	—	0.00	—	0.00	—	0.00	ns
t_RCK2RD1	RCLK-to-OUT (Pipelined)	—	1.43	—	1.63	—	1.92	ns
t_RCK2RD2	RCLK-to-OUT (Non-Pipelined)	—	2.26	—	2.58	—	3.03	ns
t_RCLKH	RCLK minimum high pulse width	0.73	—	0.73	—	0.73	—	ns
t_RCLKL	RCLK minimum low pulse width	1.89	—	1.89	—	1.89	—	ns
t_RCKP	RCLK minimum period	2.62	—	2.62	—	2.62	—	ns

Note: Timing data for these two cascaded RAM blocks uses a depth of 8,192. For all other combinations, use Microchip’s timing software.

Table 2-95. Four RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
Write Mode
t_WDASU	Write data setup vs. WCLK	—	2.37	—	2.70	—	3.17	ns
t_WDAHD	Write data hold vs. WCLK	—	0.00	—	0.00	—	0.00	ns
t_WADSU	Write address setup vs. WCLK	—	2.37	—	2.70	—	3.17	ns
t_WADHD	Write address hold vs. WCLK	—	0.00	—	0.00	—	0.00	ns
t_WENSU	Write enable setup vs. WCLK	—	2.37	—	2.70	—	3.17	ns
t_WENHD	Write enable hold vs. WCLK	—	0.00	—	0.00	—	0.00	ns
t_WCKH	WCLK minimum high pulse width	0.75	—	0.75	—	0.75	—	ns
t_WCLK	WCLK minimum low pulse width	2.51	—	2.51	—	2.51	—	ns
t_WCKP	WCLK minimum period	3.26	—	3.26	—	3.26	—	ns
Read Mode
t_RADSU	Read address setup vs. RCLK	—	3.08	—	3.51	—	4.13	ns
t_RADHD	Read address hold vs. RCLK	—	0.00	—	0.00	—	0.00	ns
t_RENSU	Read enable setup vs. RCLK	—	3.08	—	3.51	—	4.13	ns
t_RENHD	Read enable hold vs. RCLK	—	0.00	—	0.00	—	0.00	ns
t_RCK2RD1	RCLK-to-OUT (Pipelined)	—	2.36	—	2.69	—	3.16	ns
t_RCK2RD2	RCLK-to-OUT (Non-Pipelined)	—	2.83	—	3.23	—	3.79	ns
t_RCLKH	RCLK minimum high pulse width	0.73	—	0.73	—	0.73	—	ns
t_RCLKL	RCLK minimum low pulse width	2.96	—	2.96	—	2.96	—	ns
t_RCKP	RCLK minimum period	3.69	—	3.69	—	3.69	—	ns

Note: Timing data for these four cascaded RAM blocks uses a depth of 16,384. For all other combinations, use Microchip’s timing software.

Table 2-96. Eight RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
Write Mode
t_WDASU	Write data setup vs. WCLK	—	5.78	—	6.58	—	7.74	ns
t_WDAHD	Write data hold vs. WCLK	—	0.00	—	0.00	—	0.00	ns
t_WADSU	Write address setup vs. WCLK	—	5.78	—	6.58	—	7.74	ns
t_WADHD	Write address hold vs. WCLK	—	0.00	—	0.00	—	0.00	ns
t_WENSU	Write enable setup vs. WCLK	—	5.78	—	6.58	—	7.74	ns
t_WENHD	Write enable hold vs. WCLK	—	0.00	—	0.00	—	0.00	ns
t_WCKH	WCLK minimum high pulse width	0.75	—	0.75	—	0.75	—	ns
t_WCLK	WCLK minimum low pulse width	5.13	—	5.13	—	5.13	—	ns
t_WCKP	WCLK minimum period	5.88	—	5.88	—	5.88	—	ns
Read Mode
t_RADSU	Read address setup vs. RCLK	—	6.75	—	7.69	—	9.04	ns
t_RADHD	Read address hold vs. RCLK	—	0.00	—	0.00	—	0.00	ns
t_RENSU	Read enable setup vs. RCLK	—	6.75	—	7.69	—	9.04	ns
t_RENHD	Read enable hold vs. RCLK	—	0.00	—	0.00	—	0.00	ns
t_RCK2RD1	RCLK-to-OUT (Pipelined)	—	3.39	—	3.86	—	4.54	ns
t_RCK2RD2	RCLK-to-OUT (Non-Pipelined)	—	4.93	—	5.62	—	6.61	ns
t_RCLKH	RCLK minimum high pulse width	0.73	—	0.73	—	0.73	—	ns
t_RCLKL	RCLK minimum low pulse width	5.77	—	5.77	—	5.77	—	ns
t_RCKP	RCLK minimum period	6.50	—	6.50	—	6.50	—	ns

Note: Timing data for these eight cascaded RAM blocks uses a depth of 32,768. For all other combinations, use Microchip’s timing software.

Table 2-97. Sixteen RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
Write Mode
t_WDASU	Write data setup vs. WCLK	—	16.54	—	18.84	—	22.15	ns
t_WDAHD	Write data hold vs. WCLK	—	0.00	—	0.00	—	0.00	ns
t_WADSU	Write address setup vs. WCLK	—	16.54	—	18.84	—	22.15	ns
t_WADHD	Write address hold vs. WCLK	—	0.00	—	0.00	—	0.00	ns
t_WENSU	Write enable setup vs. WCLK	—	16.54	—	18.84	—	22.15	ns
t_WENHD	Write enable hold vs. WCLK	—	0.00	—	0.00	—	0.00	ns
t_WCKH	WCLK minimum high pulse width	0.75	—	0.75	—	0.75	—	ns
t_WCLK	WCLK minimum low pulse width	13.40	—	13.40	—	13.40	—	ns
t_WCKP	WCLK minimum period	14.15	—	14.15	—	14.15	—	ns
Read Mode
t_RADSU	Read address setup vs. RCLK	—	18.13	—	20.65	—	24.27	ns
t_RADHD	Read address hold vs. RCLK	—	0.00	—	0.00	—	0.00	ns
t_RENSU	Read enable setup vs. RCLK	—	18.13	—	20.65	—	24.27	ns
t_RENHD	Read enable hold vs. RCLK	—	0.00	—	0.00	—	0.00	ns
t_RCK2RD1	RCLK-to-OUT (Pipelined)	—	12.08	—	13.76	—	16.17	ns
t_RCK2RD2	RCLK-to-OUT (Non-Pipelined)	—	12.83	—	14.62	—	17.18	ns
t_RCLKH	RCLK minimum high pulse width	0.73	—	0.73	—	0.73	—	ns
t_RCLKL	RCLK minimum low pulse width	14.41	—	14.41	—	14.41	—	ns
t_RCKP	RCLK minimum period	15.14	—	15.14	—	15.14	—	ns

Note: Timing data for these sixteen cascaded RAM blocks uses a depth of 65,536. For all other combinations, use Microchip’s timing software.