2.5.3 LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit is carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The voltage swing between these two signal lines is approximately 850 mV.

Figure 2-27. LVPECL Board-Level Implementation

The LVPECL circuit is similar to the LVDS scheme. It requires four external resistors, three for the driver and one for the receiver. The values for the three driver resistors are different from that of LVDS since the output voltage levels are different. The VOH levels are 200 mV below the standard LVPECL levels.

The following table lists the DC input and output levels of LVPECL.

Table 2-63. DC Input and Output Levels
DC Parameter	Min.		Typ.		Max.		Units
DC Parameter	Min.	Max.	Min.	Max.	Min.	Max.	Units
VCCI	3		3.3		3.6		V
VOH	1.8	2.11	1.92	2.28	2.13	2.41	V
VOL	0.96	1.27	1.06	1.43	1.3	1.57	V
VIH	1.49	2.72	1.49	2.72	1.49	2.72	V
VIL	0.86	2.125	0.86	2.125	0.86	2.125	V
Differential input voltage	0.3		0.3		0.3		V

The following table lists the AC loading values.

Table 2-64. AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)	Input High (V)	Measuring Point¹ (V)
1.6 – 0.3	1.6 + 0.3	1.6

Note:

Measuring Point = VTRIP