47.4.4 Sigma-Delta Analog-to-Digital Converter (SDADC) Characteristics

Table 47-8. Operating Conditions(1)
Symbol Parameters Conditions Min Typ Max Unit
Res Resolution Differential mode - 16 - bits
Single-Ended mode - 15 -
CLK_SDADC Sampling Clock Speed 1 - 6 MHz
CLK_SDADC_FS Conversion rate CLK_SDADC/4
fs Output Data Rate Free running mode CLK_SDADC_FS / OSR
Single conversion mode

SKPCNT = N

 (CLK_SDADC_FS / OSR) x (N+1)
OSR Oversampling ratio Differential mode 64 256 1024 Cycles
Vin Input Conversion range VREF<VDDANA-0.3V

Differential mode

Gaincorr = 0x1

 - VREF - VREF V

Single-Ended mode(3)

Gaincorr = 0x1

 0 - VREF
VREF>=VDDANA-0.3V

Differential mode

Gaincorr = 0x1

 -0.7xVREF - 0.7xVREF V

Single-Ended mode(3)

Gaincorr = 0x1

 0 - 0.7xVREF
Vref Reference Voltage range 1 - VDDANA V
Vcom Common mode voltage Differential mode 0 - VDDANA V
Cin Input capacitance 0.425 0.5 0.575 pF
Zin Input impedance Differential mode 1/(Cin x CLK_SDADC_FS) kΩ
Single-Ended mode(3) 1/(Cin x CLK_SDADC_FS x 2)
Input anti-alias filter recommendation(2) Rext - 1.0 - kΩ
Cext 3.3 - 10 nF
  1. These are based on simulation. These values are not covered by test or characterization.
  2. External Anti-alias filter must be placed in front of each SDADC input to ensure high-frequency signals to not alias into measurement bandwidth. Use capacitors of X5R type for DC measurement. or capacitors of COG or NPO type for AC measurement.
  3. This mode corresponds to a differential mode where the selected AINNx pin is externally grounded.
Table 47-9. SDADC DC Performance: Differential Input Mode. Chopper ON(1)
Symbol Parameters Conditions (2) Min Typ Max Unit
INL Integral Non Linearity CLK_SDADC = 3MHz VREF = 1.2V - +/-2.9 +/-3.9 LSB
CLK_SDADC = 3MHz INT VREF = 5.5V - +/-8.4 +/-9.3
DNL Differential Non Linearity CLK_SDADC = 3MHz VREF = 1.2V - +/-1.5 +/-2.1 LSB
CLK_SDADC = 3MHz INT VREF = 5.5V - +/-1.7 +/-2.3
Eg Gain Errors CLK_SDADC = 3MHz VREF = 1.2V - +/-0.3 +/-1.9 %
CLK_SDADC = 3MHz INT VREF = 5.5V - +/-0.3 +/-1.7
TCg Gain Drift CLK_SDADC = 3MHz VREF = 1.2V -0.9 3.9 17.5 ppm/°C
Off Offset Error CLK_SDADC = 3MHz VREF = 1.2V - +/-2.3 +/-3.7 mV
CLK_SDADC = 3MHz INT VREF = 5.5V - +/-0.3 +/-2.4
Tco Offset Error Drift CLK_SDADC = 3MHz VREF = 1.2V -1.4 0.01 0.6 uV/°C
  1. OSR=256
Table 47-10. SDADC DC Performance: Differential Input Mode. Chopper OFF(1)
Symbol Parameters Conditions (2) Min Typ Max Unit
INL Integral Non Linearity CLK_SDADC = 6MHz VREF = 1.2V - +/-5.5 +/-9.3 LSB
CLK_SDADC = 6MHz INT VREF = 5.5V - +/-8.9 +/-10.1
DNL Differential Non Linearity CLK_SDADC = 6MHz VREF = 1.2V - +/-2.8 +/-4.1 LSB
CLK_SDADC = 6MHz INT VREF = 5.5V - +/-1.8 +/-3
Eg Gain Errors CLK_SDADC = 6MHz VREF = 1.2V - +/-0.6 +/-2.1 %
CLK_SDADC = 6MHz INT VREF = 5.5V - +/-0.3 +/-1.7
TCg Gain Drift CLK_SDADC = 6MHz VREF = 1.2V -19.7 2.2 20.9 ppm/°C
Off Offset Error CLK_SDADC = 6MHz VREF = 1.2V - +/-1.7 +/-14.3 mV
CLK_SDADC = 6MHz INT VREF = 5.5V - +/-4.9 +/-13.2
Tco Offset Error Drift CLK_SDADC = 6MHz VREF = 1.2V -14 12.4 60 μV/°C
Input noise rms AC Input noise rms OSR = 256 VREF = 1.2V - 19 20
OSR = 256 VREF = 5.5V - 59 76 mVrms
  1. OSR=256
Table 47-11. SDADC AC Performance: : Differential Input Mode(1)
Symbol Parameters Conditions (2) Min Typ Max Unit
ENOB Effective Number Of Bits Ext ref = 1.2V 12 15.3 15.4 bits
Int Ref = 5.5V 12.9 13.1 14
DR Dynamic Range Ext ref = 1.2V 90.5 92.4 93.2 dB
Int Ref = 5.5V 83.0 95.6 97.0
SNR Signal to Noise Ratio Ext ref = 1.2V 68.7 88.7 89 dB
Int Ref = 5.5V 83 95.6 97
SINAD Signal to Noise + Distortion Ratio Ext ref = 1.2V 71.1 90.7 91.7 dB
Int Ref = 5.5V 77.1 78.6 83.2
THD Total Harmonic Distortion Ext ref = 1.2V -102.3 -94.6 -75.3 dB
Int Ref = 5.5V -99.9 -94.7 -85.4
  1. Values based on characterization.
  2. OSR=256, Chopper OFF, Sampling Clock Speed at 6MHz.