Note: This register is write-synchronized:
SYNCBUSY.CC[n] must be checked to ensure the CC[n] register synchronization is complete.
Name:
CCBUF[n]
Offset:
0x30 + n*0x01 [n=0..1]
Reset:
0x00
Property:
Write-Synchronized
Bit
7
6
5
4
3
2
1
0
CCBUF[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 7:0 – CCBUF[7:0] Channel Compare
Buffer Value
This bit field holds
the value of the Channel n Compare Buffer Value. When the buffer valid flag is
‘1’ and double buffering is enabled (CTRLBCLR.LUPD = 1), the data
from buffer registers will be copied into the corresponding CC[n] register under UPDATE
condition, including the software update command
(CTRLBSET.CMD=0x3).
DS40002667A
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