33.4.5 Debug Operation

When the CPU is halted in debug mode, the ADC will halt normal operation. Setting the Debug Run bit in the Debug Control register (DBGCTRL.DBGRUN) forces the ADC to continue operating while the CPU is halted in debug mode. Refer to Table 33-7 for details on ADC behavior based on the mode of operation and the configuration of the DBGRUN bit.

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