25.4.7 SSPxCON3
Note:
- For daisy-chained SPI operation;
allows the user to ignore all except the last received byte. SSPOV is still set
when a new byte is received and BF =
1, but hardware continues to write the most recent byte to SSPxBUF.
| Name: | SSPxCON3 |
| Offset: | 0x0192 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ACKTIM | PCIE | SCIE | BOEN | SDAHT | SBCDE | AHEN | DHEN | ||
| Access | R/HS/HC | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – ACKTIM
| Value | Name | Description |
|---|---|---|
| x | SPI or I2C Host | This bit is not used |
| 1 | I2C Client and AHEN = 1 or DHEN =
1 |
Eighth falling edge of SCL has occurred and the ACK/NACK state is Active |
| 0 | I2C Client | ACK/NACK state is not Active. Transitions low on ninth rising edge of SCL. |
Bit 6 – PCIE
| Value | Name | Description |
|---|---|---|
| x | SPI or SSPM = 1111 or
1110 |
This bit is not used |
| 1 | SSPM ≠ 1111 and SSPM ≠
1110 |
Enable interrupt on detection of Stop condition |
| 0 | SSPM ≠ 1111 and SSPM ≠
1110 |
Stop detection interrupts are disabled |
Bit 5 – SCIE Start Condition Interrupt Enable bit
| Value | Name | Description |
|---|---|---|
| x | SPI or SSPM = 1111 or
1110 |
This bit is not used |
| 1 | SSPM ≠ 1111 and SSPM ≠
1110 |
Enable interrupt on detection of Start condition |
| 0 | SSPM ≠ 1111 and SSPM ≠
1110 |
Start detection interrupts are disabled |
Bit 4 – BOEN
| Value | Name | Description |
|---|---|---|
| 1 | SPI | SSPxBUF is updated every time a new data byte is available, ignoring the BF bit |
| 0 | SPI | If a new byte is receive with BF set then SSPOV is set and SSPxBUF is not updated |
| 1 | I2C | SSPxBUF is updated every time a new data byte is available, ignoring the SSPOV effect on updating the buffer |
| 0 | I2C | SSPxBUF is only updated when SSPOV is clear |
Bit 3 – SDAHT SDA Hold Time Selection bit
| Value | Name | Description |
|---|---|---|
| x | SPI | Not used in SPI mode |
| 1 | I2C |
Minimum of 300 ns hold time on SDA after the falling edge of SCL |
| 0 | I2C |
Minimum of 100 ns hold time on SDA after the falling edge of SCL |
Bit 2 – SBCDE Client Mode Bus Collision Detect Enable bit
Unused in Host mode.
| Value | Name | Description |
|---|---|---|
| x | SPI or I2C Host | This bit is not used |
| 1 | I2C Client | Bus Collision detection is enabled |
| 0 | I2C Client | Bus Collision detection is not enabled |
Bit 1 – AHEN Address Hold Enable bit
| Value | Name | Description |
|---|---|---|
| x | SPI or I2C Host | This bit is not used |
| 1 | I2C Client | Address hold is enabled. As a result, CKP is cleared after the eighth falling SCL edge of an address byte reception. Software must set the CKP bit to resume operation. |
| 0 | I2C Client | Address hold is not enabled |
Bit 0 – DHEN Data Hold Enable bit
| Value | Name | Description |
|---|---|---|
| x | SPI or I2C Host | This bit is not used |
| 1 | I2C Client | Data hold is enabled. As a result, CKP is cleared after the eighth falling SCL edge of a data byte reception. Software must set the CKP bit to resume operation. |
| 0 | I2C Client | Data hold is not enabled |