High-Performance dsPIC33A DSP/CISC CPU
- 32-bit Rich Instruction Set for
Optimized Speed and Program Code Size
- 16-bit dsPIC33 core compatible
- Non-paged linear data/Flash 24-bit addressing space
- 16-bit/32-bit instructions for optimized code size and performance
- 32-Bit Wide Data Paths
- Single and Double Precision Floating-Point Unit (FPU) Coprocessor
- 2-Kbyte Instruction Cache
- Sixteen 32-Bit Working Registers
- Dual 72-Bit Accumulators Supporting 32-Bit and 16-Bit Fixed-Point DSP Operations
- Eight Level Deep Working Register Sets
- Eight Level Deep Accumulator Register Sets
- Eight Level Deep Floating-Point Register Sets