1 Peripheral Overview

The APM allows analog modules to be periodically switched on and off using dedicated timers without requiring CPU cycles. This feature is useful for low-power applications that use analog sensors and require optimization of the total power consumption. The APM allows the users to set custom time intervals in which the configured analog modules will periodically activate to perform a specified function before deactivating and returning to a low-power state after the programmed time has elapsed. The APM can be used to switch on and off peripherals such as:

  • Zero-Cross Detect peripheral (ZCD)
  • Analog Comparator peripheral (CMP)
  • Digital-to-Analog Converter peripheral (DAC)
  • Operational Amplifier peripheral (OPA)
  • Temperature Indicator peripheral (TEMP)
  • Analog-to-Digital Converter peripheral (ADC)
  • Fixed Voltage Reference peripheral (FVR)
  • Band Gap Reference peripheral (BG)

Depending on the device family, the list of examples mentioned above may include more or fewer analog modules.

The APM utilizes an integrated 16-bit timer with a 16-bit prescaler to control the frequency in which the specified analog peripherals will be activated and deactivated. This timer can be clocked using a range of sources, such as:

  • LFINTOSC (31 kHz)
  • SOSC (32.768 kHz)
  • ADCRC
  • External clock source connected to a dedicated Peripheral Pin select (PPS) input pin.

The APM allows the user to group the analog modules into two different Start (S1/S2) and End (E1/E2) time events and provides the flexibility to configure which of those modules will be enabled and disabled during each respective event. This feature is achieved by having dedicated peripheral control registers for all time events.

Once the APM has been enabled, the 16-bit timer will begin counting based on the programmed period and prescaler. When the period counter matches the value specified by the Start 1 event, the APM enables the specified analog peripherals using the APMPERS1 register. Once this happens, a secondary 24-bit internal offset counter, with no prescaler, will begin counting. This offset counter is used to determine the timings for the subsequent End 1, Start 2 and End 2 events.

The subsequent events differ from Start 1, in that the values specified by those events are compared to the 24-bit offset counter instead of the 16-bit APM period with prescaler counter. Once the offset counter matches the value specified for each respective APM event timing configuration register, the APM will disable or enable the specified analog peripherals. When the offset counter matches the value specified by the End 2 event, the configured peripherals will be disabled and the 24-bit internal offset counter is stopped and reset until it is reactivated when a Start 1 event occurs again.

The design of the APM module makes it such that the very first event that will always occur is a Start 1 event, but there are no hardware restrictions preventing an End 2 event from occurring before an End 1 event. The user must take care when configuring the event timing of the APM module; if the Start 2 or End 1 events are programmed to occur after the End 2 event, they will never take place as the offset counter would be stopped when the End 2 event occurs, and the other event timing matches would never take place.

A main feature of the APM is that when clocked by LFINTOSC (Low Frequency Internal Oscillator), which is the slowest internal clock source available to the APM, the 16-bit period counter with 16-bit prescaler provides a maximum period of approximately 38.4 hours before overflowing, while the 24-bit offset counter provides a maximum time interval of approximately 541.2 seconds in which the analog peripherals can be switched on and off. This feature offers a high level of flexibility to the user and accommodates for a wide range of low-power applications which require analog peripherals usage.

The APM can be used to periodically activate the Analog-to-Digital Converter (ADC) peripheral to control the timing in which the conversions are performed. The ADC is unique in comparison to the other analog modules that can be controlled by the APM, as it has separate Peripheral Start and Stop Enable bits for the analog (ADCA) and digital (ADCD) portions of the peripheral.

Setting the ADCA Peripheral Start bit will allow the APM to enable the ADC module and the analog references needed when the respective Start Event occurs and prepare it to perform conversions. Setting the ADCD Peripheral Start bit will allow the APM to activate the digital portion of the ADC and trigger a conversion when the respective Start Event occurs. The user must select the APM as the Auto-Conversion Trigger source when configuring the ADC in order for the APM to be capable of automatically triggering conversions.

The user must take the following points into consideration when configuring the ADCA and ADCD Start and End events.

  • The ADCA Start event must occur before the ADCD Start event to ensure the analog portion of the ADC peripheral has been enabled and initialized before a conversion is triggered.
  • The user must ensure enough time has lapsed after an ADCA Start event to allow the ADC to stabilize before a conversion is triggered by an ADCD Start event.
  • The user must ensure enough time has lapsed after an ADCD Start event to account for the complete ADC conversion time before the ADC is disabled by the APM. If the APM is configured to disable either the analog or digital portions of the ADC before a conversion is completed, the results may be incorrect.
  • The ADCA and ADCD End events can both occur at the same time once the ADC conversion has been completed.
Figure 1-1. APM Functional Block Diagram

Considering the operating principle of the APM, which is based on counter timers matching specified enable and disable timings for different analog peripherals, to obtain the desired functionality of the application, the user must take into consideration the following observations when configuring the APM:

  • The Start 2 event must always occur before the End 2 event (S2 < E2). Otherwise, the Start 2 event will never occur as the offset counter is stopped and reset on a match with the End 2 event.
  • The End 1 event must always occur before or at the same time with the End 2 event (E1 <= E2). Otherwise, the End 1 event will never occur as the offset counter is stopped and reset on a match with the End 2 event.
  • In the specific case where the Start 1 event is programmed to occur as soon as the period counter is started (S1 = 0s), the End 2 event must always occur before the end of the APM period (E2 < PER). This condition is required to avoid the case where the period counter resets and matches the Start 1 event timing before the offset counter manages to reset after matching the End 2 event timing from the previous period. This situation causes the offset counter to “miss” the enable signal generated by the match between the period counter and the Start 1 event timing and results in the subsequent events not occurring for the ongoing period.
  • In the case Start 1 event was programmed to occur after the period counter started (S1 > 0s), for the user to obtain the desired behavior, the sum between Start 1 and End 2 event timings must be equal to or less than the APM period ([S1 + E2] <= PER). This condition is required to obtain the event timings and periodicity specified by the user.
Note: The scenario where S1 = 0s only works as intended when the prescaler is 0 which translates to a maximum period of 2.115s when the APM is clocked with LFINTOSC.