Introduction

The PIC18F26/46/56Q71 devices that you have received conform functionally to the current device data sheet (DS40002329F), except for the anomalies described in this document.

The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in the table below.

The errata described in this document will be addressed in future revisions of the PIC18F26/46/56Q71 silicon.

Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current.

Table . Silicon Device Identification
Part Number	Device ID	Revision ID
Part Number	Device ID	A2	A3	A4
PIC18F26Q71	0x76E0	0xA002	0xA003	0xA004
PIC18F46Q71	0x7720	0xA002	0xA003	0xA004
PIC18F56Q71	0x7760	0xA002	0xA003	0xA004

Important: Refer to the Device/Revision ID section in the current “PIC18-Q71 Family Programming Specification” (DS40002306) for more detailed information on Device Identification and Revision IDs for your specific device.

Table . Silicon Issue Summary
Module	Feature	Item No.	Issue Summary	Affected Revisions
Module	Feature	Item No.	Issue Summary	A2	A3	A4
Universal Timer Module	Level-Triggered ERS Start/Reset condition	Dead Zone Exists in Level-Triggered Start/Reset Condition When an ERS Signal Is Generated Due to an SFR Access	Dead zone exists in level-triggered Start/Reset condition when ERS signal is generated due to an SFR access	X	X	X
	Clear Command	Clear Command May Not Work Properly in Asynchronous Mode	Clear command may not work properly	X
	Interrupts	Interrupts Do Not Work When Leaving Debug Mode	Interrupts do not work after leaving Debug mode	X	X	X
In-Circuit Serial Programming™	Low-Voltage Programming	Low-Voltage Programming Not Possible	Low-Voltage Programming is not possible when V_DD is below BORV while BOR is enabled	X	X	X
Electrical Specifications	Maximum Input Leakage Current	Increased Maximum Input Leakage Current Specification on 8-bit Digital-to-Analog Converter (DAC) V_REF- Pins	Increased maximum Input Leakage Current specification on 8-bit Digital-to-Analog Converter (DAC) V_REF- pins	X
Universal Asynchronous Receiver Transmitter	UART	UART TXDE Signal May Go Low before the STOP Bit Has Been Entirely Transmitted	UART TXDE signal may go low before the Stop bit has been entirely transmitted	X	X	X
PIC18 Core	FSR Shadow Registers	FSR Shadow Registers Are Not Writable	FSR Shadow Registers are not writable	X	X	X
I²C	Host Data Request (MDR) Bit	MDR Bit Is Not Cleared after Bus Time-Out	MDR bit is not cleared after Bus Time-Out	X	X	X
	Bus Time-Out	Bus Time-Out Not Detected Properly When External Host Clock Stretches	Bus Time-Out not detected properly when External Host Clock stretches	X	X	X
	Clock Stretch Disable	Clock Stretch Disable Not Working Properly	Clock Stretch Disable not working properly	X	X	X
	Bus Time-Out	Bus Time-Out Causes False Start/Stop	Bus Time-Out causes false Start/Stop	X	X	X
	Multi-Host Mode	Operating in Multi-Host Mode Will Cause Bus Failures	Multi-Host Mode will cause Bus failures	X	X	X
	Bus Time-Out	CSTR Bit Is Not Cleared after Bus Time-Out	CSTR bit is not cleared after Bus Time-Out	X	X	X
	Bus Collision	Bus Collision Followed by a Stop Condition during a Transaction by an External Host Device May Hang the Bus	Bus Collision followed by a Stop condition during a transaction by an external Host device may hang the bus	X	X	X
	Bus Free Time	The Bus Free Divider Ratio BFREDR = 1 Value Is Not Functional	I²C - the Bus Free Divider Ratio BFREDR = 1 value is not functional	X	X	X
	Multi-Host Arbitration	I²C Module May Hang the Bus During Multi-Host Arbitration	I²C module may hang the bus during Multi-Host Arbitration	X	X	X
CMP - Comparator	CMP	Comparator Module Will Not Function in ULP Mode	Comparator module will not function in ULP mode	X	X	X
Timer1	Timer1 Gate Source	Changing the Timer1 Gate Source May Cause Unexpected Interrupts	Changing the Timer1 Gate Source may cause unexpected interrupts	X	X	X
Note: Only those issues indicated in the last column apply to the current silicon revision.