24.8.4 CLCnSEL0

Generic CLCn Data 1 Select Register
Name: CLCnSEL0
Address: 0x0D8

Bit 76543210 
   D1S[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset xxxxxx 

Bits 5:0 – D1S[5:0] CLCn Data1 Input Selection

Table 24-2. CLC Input Selection
DyS Input Source DyS (cont.) Input Source (cont.) DyS (cont.) Input Source (cont.)
[0] 0000 0000 CLCIN0PPS [20] 0001 0100 TMR2 [40] 0010 1000 CLC4
[1] 0000 0001 CLCIN1PPS [21] 0001 0101 TMR3 [41] 0010 1001 CLC5
[2] 0000 0010 CLCIN2PPS [22] 0001 0110 TMR4 [42] 0010 1010 CLC6
[3] 0000 0011 CLCIN3PPS [23] 0001 0111 CCP1 [43] 0010 1011 CLC7
[4] 0000 0100 CLCIN4PPS [24] 0001 1000 CCP2 [44] 0010 1100 CLC8
[5] 0000 0101 CLCIN5PPS [25] 0001 1001 PWM1S1P1_OUT [45] 0010 1101 U1TX
[6] 0000 0110 CLCIN6PPS [26] 0001 1010 PWM1S1P2_OUT [46] 0010 1110 U2TX
[7] 0000 0111 CLCIN7PPS [27] 0001 1011 PWM2S1P1_OUT [47] 0010 1111 SPI1_SDO
[8] 0000 1000 FOSC [28] 0001 1100 PWM2S1P2_OUT [48] 0011 0000 SPI1_SCK
[9] 0000 1001 HFINTOSC(1) [29] 0001 1101 PWM3S1P1_OUT [49] 0011 0001 SPI1_SS
[10] 0000 1010 LFINTOSC(1) [30] 0001 1110 PWM3S1P2_OUT [50] 0011 0010 I2C_SCL
[11] 0000 1011 MFINTOSC(1) [31] 0001 1111 NCO1 [51] 0011 0011 I2C_SDA
[12] 0000 1100 MFINTOSC (31.25 kHz)(1) [32] 0010 0000 CMP1_OUT [52] 0011 0100 CWG1A
[13] 0000 1101 SFINTOSC (1 MHz)(1) [33] 0010 0001 CMP2_OUT [53] 0011 0101 CWG1B
[14] 0000 1110 SOSC(1) [34] 0010 0010 ZCD [54] 0011 0110 TU16A
[15] 0000 1111 EXTOSC(1) [35] 0010 0011 IOC [55] 0011 0111 TU16B
[16] 0001 0000 ADCRC(1) [36] 0010 0100 HLVD_OUT ... —
[17] 0001 0001 CLKR [37] 0010 0101 CLC1 ... —
[18] 0001 0010 TMR0 [38] 0010 0110 CLC2 ... —
[19] 0001 0011 TMR1 [39] 0010 0111 CLC3 [63] 0011 1111 —
Note:
  1. Requests clock.
Reset States: 
POR/BOR = xxxxxx
All Other Resets = uuuuuu