4.1 Revision History


Doc Rev.	Date	Comments
C	07/2021	“Affected Silicon Revisions” of erratum CCMP and CNT Registers Operate as 16-Bit Registers in 8-Bit PWM Mode is corrected Added Errata: The CCL Must be Disabled to Change the Configuration of a Single LUT Added data sheet clarifications: Ordering Information - Automotive Ordering Codes Are Available on Request
B	02/2021	Added new errata: Device: Revision History TCA: Restart Will Reset Counter Direction in NORMAL and FRQ Mode TCB: CCMP and CNT Registers Operate as 16-Bit Registers in 8-Bit PWM Mode USART: Open-Drain Mode Does Not Work When TXD is Configured as Output Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode New hold place for CPUINT errata: After Device errata
A	01/2020	Document Change document structure from one document for the entire megaAVR 0-series to one document per data sheet: from: megaAVR-0-series-Errata-and-Clarification-80000777C.pdf to: ATmega4808_4809-Errata-and-Clarification-DS80000867A.pdf Updated document template Errata The ADC errata, ADC Functionality Cannot be Ensured with ADCCLK Above 1.5 MHz for All Conditions, has been split into two separate erratas and rewritten

ATmega4808/4809