Management of the Embedded Voltage Regulator to Enter In and Exit from Backup Mode
Management of Supply Monitors on VDD3V3 and VDDCORE to Trigger a
Reset
Shutdown Logic for External VDDCORE Generation
Software assertion of the Shutdown Output pin (SHDN)
Automatic de-assertion from the configurable wake-up events
Slow Clock Generation
MD_SLCK—Monitoring domain slow clock. This clock, sourced from the Slow RC oscillator, is the only permanent clock of the system and feeds the safety-critical functions of the device (WDT, RSTC, SUPC, frequency monitors and detectors, PMC start-up time counters). Its source cannot be modified.
TD_CLK—Timing domain slow clock. This clock, generally sourced from the 32.768 kHz crystal oscillator, is routed to the RTC and RTT peripherals.
Independent Tamper Detection on 5 Inputs with Configurable Backup Mode Exit
Programmable Immediate Clear of the General-Purpose Backup Registers (GPBR) on Tamper Events
Support of Multiple Wake-Up Sources to Exit from Backup Mode
15 wake-up inputs with programmable debouncers
Real-Time Clock alarm
Real-Time Timer alarm
Supply monitor detection on VDD3V3, with programmable sampling
period and voltage threshold
Detection of VDDCORE rising edge when externally supplied
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