49.6 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	UART_CR	31:24
		23:16
		15:8		OPT_SLEEP		REQCLR	STTTO	RETTO		RSTSTA
		7:0	TXDIS	TXEN	RXDIS	RXEN	RSTTX	RSTRX
0x04	UART_MR	31:24		OPT_CMPTH[2:0]				OPT_DUTY[2:0]
		23:16				OPT_CLKDIV[4:0]
		15:8	CHMODE[1:0]			BRSRCCK	PAR[2:0]			OPTI_WKUP
		7:0	EDGESEL[1:0]		ACON	FILTER	OPT_DMOD	OPT_MDINV	OPT_RXINV	OPT_EN
0x08	UART_IER	31:24
		23:16								ACE
		15:8	CMP			RXBUFF	TXBUFE		TXEMPTY	TIMEOUT
		7:0	PARE	FRAME	OVRE	ENDTX	ENDRX		TXRDY	RXRDY
0x0C	UART_IDR	31:24
		23:16								ACE
		15:8	CMP			RXBUFF	TXBUFE		TXEMPTY	TIMEOUT
		7:0	PARE	FRAME	OVRE	ENDTX	ENDRX		TXRDY	RXRDY
0x10	UART_IMR	31:24
		23:16								ACE
		15:8	CMP			RXBUFF	TXBUFE		TXEMPTY	TIMEOUT
		7:0	PARE	FRAME	OVRE	ENDTX	ENDRX		TXRDY	RXRDY
0x14	UART_SR	31:24
		23:16								ACE
		15:8	CMP			RXBUFF	TXBUFE		TXEMPTY	TIMEOUT
		7:0	PARE	FRAME	OVRE	ENDTX	ENDRX		TXRDY	RXRDY
0x18	UART_RHR	31:24
		23:16
		15:8
		7:0	RXCHR[7:0]
0x1C	UART_THR	31:24
		23:16
		15:8
		7:0	TXCHR[7:0]
0x20	UART_BRGR	31:24
		23:16
		15:8	CD[15:8]
		7:0	CD[7:0]
0x24	UART_CMPR	31:24
		23:16	VAL2[7:0]
		15:8		CMPPAR		CMPMODE
		7:0	VAL1[7:0]
0x28	UART_RTOR	31:24
		23:16
		15:8
		7:0	TO[7:0]
0x2C	UART_CSR	31:24
		23:16
		15:8
		7:0								ACO
0x30 ... 0xE3	Reserved
0xE4	UART_WPMR	31:24	WPKEY[23:16]
		23:16	WPKEY[15:8]
		15:8	WPKEY[7:0]
		7:0								WPEN
0xE8 ... 0xFF	Reserved
0x0100 ... 0x128	Reserved for PDC registers	31:24
		23:16
		15:8
		7:0