24.1 Description

The System Controller embeds 768 bits of General Purpose Backup registers organized as 24 32-bit registers.

It is possible to generate an immediate clear of the content of General Purpose Backup registers 0 to 11 (first half), if a tamper event is detected on one of the tamper pins, TMP0 to TMP4 by writing RTC_TCR.TAMPCLR to ‘1’. The content of the other General Purpose Backup registers (second half) remains unchanged.

The immediate clear on tamper detection can be extended to all General Purpose Backup registers by writing RTC_TCR.FGPBRCLR to ‘1’.

It is also possible to generate an immediate clear of all General Purpose Backup registers if the embedded Flash is erased by writing SUPC_EMR.FLRSGPBR to ‘1’ in the Supply Controller.

SYS_GPBR0 to SYS_GPBR15 can be individually (each 32-bit part-select) read- and write-protected by configuring GPBR_MR. This register is write-once, which means that once it has been configured, the read or write protection is available until the loss of VDDBU.