33.2 Embedded Characteristics

  • Physically Addressed and Physically Tagged
  • L1 Data Cache Set to 16/8 Kbytes
  • L1 Cache Line Size Set to 16 bytes
  • L1 Cache Integrates 32 System Bus Interface
  • Unified Direct Mapped Cache Architecture
  • Unified 4-way Set Associative Cache Architecture
  • Write Accesses Forwarded, Cache State Not Modified. Allocate On Read.
  • Round Robin Victim Selection Policy
  • Event Monitoring, with One Programmable 32-bit Counter
  • Configuration Registers Accessible through Cortex-M Private Peripheral Bus (PPB)
  • Cache Interface Includes Cache Maintenance Operations Registers
  • Register Write Protection