22.6.12 RTC Interrupt Enable Register
This register can only be written if the WPITEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
| Name: | RTC_IER |
| Offset: | 0x20 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | TDERREN | CALEN | TIMEN | SECEN | ALREN | ACKEN | |
| Access | | | W | W | W | W | W | W | |
| Reset | | | – | – | – | – | – | – | |
Bit 5 – TDERREN Time and/or Date Error Interrupt Enable
If the RTC is
configured in UTC mode, this bit has no effect.
Bit 4 – CALEN Calendar Event Interrupt Enable
If the RTC is
configured in UTC mode, this bit has no effect.
Bit 3 – TIMEN Time Event Interrupt Enable
If the RTC is
configured in UTC mode, this bit has no effect.
Bit 2 – SECEN Second Event Interrupt Enable
Bit 1 – ALREN Alarm Interrupt Enable
Bit 0 – ACKEN Acknowledge Update Interrupt Enable
