5 PoDL Evaluation Measurements

To verify the results of the simulations and to check the behavior of the systems in a real environment, the evaluations were repeated using real hardware in a laboratory environment. The same topologies and couplings were used, and the same values for the components were used. The results of the simulations will be compared to the results of these measurements.

Figure 5-1 below shows the results from the measurement of the same configuration that was simulated previously. The resulting eye diagram and jitter plot of the measurements are nearly identical to the simulation results.

Figure 5-1. Measurements using two 47 µH single inductors on Topology 1

Figure 5-2 below shows the results of the measurement of the second system that was simulated. Again, the resulting eye diagram and jitter plot are not exactly equal, but still very close to the results of the simulation.

Figure 5-2. Measurements using two 68 µH separate inductors on Topology 3

In both the simulation and measurement, the second system shows much worse noise and jitter performance than the first system. However, despite this, both systems are fully functional. The second example is used as a worst care analysis of the results. An important thing to note is that the amount of external or alien noise will greatly affect the system. In a high noise environment, a high alien noise tolerance is required for the system to work properly. On the other hand, if the system is employed in an environment with little external noise, it will still remain functional even with a very low noise tolerance. Therefore, to make a valid prediction about the functionality of the system the level of alien noise must also be known.

Finally, the setup for an eight node system was tested. The topology is the same that was simulated previously. The results of the eight node measurement are shown below in Figure 5-3. The Alien Noise and Jitter Tolerance plot shows that the system has some noise tolerance left over. If the environment the system is placed in does not have too much noise, it will function correctly.

Figure 5-3. Measurements using 47 µH coupled Inductors on 8 Node Topology

Table 5-1 below shows some of the inductors used in testing. One of the biggest issues when using single inductor pairs is finding equally matched inductors for each device. Using matched inductors is recommended to keep the symmetry of the differential line. If different value inductors are used, the eye diagram for the particular node will not be symmetric, reducing noise margin. Furthermore, the inductors used are only rated for a relatively low current. This may be acceptable for each PD, since it requires little power individually, but this will become an issue for the PSE when it will need to power each device simultaneously. Measurements and tests also showed that the tolerance of the components can play a major role on the workability of the solution. A minimum inductance on each node is required. If the actual inductance falls below this because the components tolerance is too high, then the system might be more susceptible to external noise.

Table 5-1. Component Used during Testing
ArchitectureNominal Inductance (µH)Saturation Current (mA)Rated Current (mA)DC Resistance (mΩ)Tolerance (%)
DMC47300250806±20
Single Inductors151100850252±20
Single Inductors47700-660±20
Single Inductors68760-420±20
Coupled Inductors471375900300±20
Coupled Inductors6822201220230±20
Coupled Inductors47-1440174±20

Power Consumption

While taking the measurements during the tests described above, the connected nodes were powering the local microcontrollers. While not measuring the power consumption of each individual node, the total power consumption of the system was measured instead. The results are shown below in Table 5-2.

Table 5-2. Measured Power Consumption of System Configurations
Number of nodesNetwork Supply VoltageTotal current
212V160 mA
512V480 mA
812V740 mA

Additional measurements were done for the eight node system. For this system, a load variation test was conducted. During this test, one node draws additional power to simulate cyclic power consumption of an application or transmission. To test this, a dynamic load was applied on the low voltage side of the power regulator. This dynamic load was implemented by adding a 13 Ω resistance parallel to the rest of the node. This extra load resembled a sawtooth signal, where the current drawn steadily increased to the maximum and then rapidly returned to zero. The frequency of the signal was changed and is shown below in Table 5-3. During these tests, the system was monitored to see if this has an impact on the noise created in the system and if communication between nodes is still possible. During any of these tests, no communication was lost and the nodes were able to transfer data as normal. No major impact on noise behavior was detected. The results of these tests are shown below.

Table 5-3. Load Variations for Eight Node System
Load Variation FrequencyNetwork Supply VoltageTotal Maximum Current
77 Hz12V955 mA
778 Hz12V962 mA
180 kHz12V1004 mA