2.4.1 Nested Interrupts During Flash Erase/Write May Cause Lower Level Interrupts to be Ignored
When a Flash erase or write operation is ongoing, nested interrupts can cause the interrupt execution status bits (LVL1EX or LVL0EX in CPUINT.STATUS) to be permanently set, causing lower level interrupts to be ignored.
Work Around
During Flash erase or write operation, do not enable level 1 interrupt (LVL1VEC = '0' in CPUINT.LVL1VEC) or Non-Maskable Interrupt. Note that NMI sources can be enabled if the NMI routine will trigger a reset of the device.
Affected Silicon Revisions
A3
X
DS80001116C
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