54.13.5 Fractional Digital Phase Lock Loop (FDPLL) Characteristics

Table 54-53. Fractional Digital Phase Lock Loop Characteristics (2)
SymbolParameterConditionsMin.Typ.Max.Units
fIN(1)Input Frequency 32-3200kHz
fOUT(1)Output Frequency 96-200MHz
Jp Period jitter (Peak-Peak value)fIN = 32 kHz, fOUT = 96 MHz -1.9 2.7%
fIN = 32 kHz, fOUT = 200 MHz -3.4 4.9
fIN = 3.2 MHz, fOUT = 96 MHz -2.0 3.0
fIN = 3.2 MHz, fOUT = 200 MHz -4.3 6.6
tLOCK Lock TimeAfter startup, time to get lock signal. fIN = 3.2 MHz-54 95μs
Duty (1)Duty cycle --50-%
Note:
  1. These values are based on simulation. They are not covered by production test limits or characterization.
  2. These FDPLL200Mn characteristics are applicable with LDO regulator and a direct reference (i.e., REFCLK is XOSC or XOSC32K, not GCLK).
Table 54-54. Fractional Digital Phase Lock Loop Power Consumption
SymbolParameterConditionsTATyp.Max.Units
IDDCurrent Consumption Clk = 96 MHz, VDD = 3.3VMax. 85°C

Typ. 25°C

0.91.3mA
Clk = 200 MHz, VDD = 3.3V22.3