13.7 Clocks after Reset

On any Reset the synchronous clocks start to their initial state:

• DFLL48M is enabled and configured to run at 48MHz
• Generic Generator 0 uses DFLL48M as source and generates GCLK_MAIN
• CPU and BUS clocks are undivided

On a Power-on Reset, the 32KHz clock sources are reset and the GCLK module starts to its initial state:

• All Generic Clock Generators are disabled except
  • Generator 0 is using DFLL48M at 48MHz as source and generates GCLK_MAIN
• All Peripheral Channels in GCLK are disabled.

On a User Reset the GCLK module starts to its initial state, except for:

• Generic Clocks that are write-locked, i.e., the according WRTLOCK is set to 1 prior to Reset