54.10.4 Analog-to-Digital Converter (ADC) Characteristics

Table 54-22. ADC Electrical Specifications (1)
AC CHARACTERISTICSStandard Operating Conditions: VDDIO=VDDANA 1.71V to 3.63V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param. No.SymbolCharacteristicsMin.TypicalMax.UnitsConditions
Device Supply
ADC1VDDANAADC Module SupplyVDDANA(min)—VDDANA(max)VVDDIOx = VDDANA
Reference Inputs
ADC3VREFADC Reference Voltage 1—VDDANA-0.4VInternal or External Reference VREF ≤ VDDANA - 0.4V
Analog Input Range
ADC7AFSFull-Scale Analog Input Signal Range (Single-Ended)GNDANA—VREFV
ADC9Full-Scale Analog Input Signal Range (Differential)-VREF—+VREFV
ADC11VCMInput common mode voltage0 VDDANAVCTRLA.R2R =1
See Note2 CTRLA.R2R =0
ADC13TSETTINGADC stabilization Time—10—µsCTRLA.ENABLE=1 or CTRLA.ONEDEMAND=1
Note:
  1. These values are based on simulation. They are not covered by production test limits or characterization.

  2. Limit the input common mode voltage using the following equations (where, VCM_IN is the input channel common mode voltage):

    When CTRLA.R2R = 0:

    • VCM_IN < 0.75*VREF
    • VCM_IN > Maximum of (0, VREF-VDDANA-0.7, 1.25*VREF-VDDANA)
Figure 54-4. ADC Analog Input AINx
The minimum sampling time tsamplehold for a given Rsource can be found using a general formula:
tsamplehold≥(Rsample+Rsource)×Csample×(n+2)×ln⁡(2)

For 12-bit accuracy, this turns into:

tsamplehold≥(Rsample+Rsource)×Csample×9.7
Table 54-23. ADC Conversion Timing Requirements(4)
AC CHARACTERISTICSStandard Operating Conditions: VDDIO=VDDANA 1.71V to 3.63V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C
Param. No.SymbolCharacteristicsMin.TypicalMax.UnitsConditions
ADC Clock Requirements
ADC21TADADC Clock Period62.5—6250ns
ADC23fGCLK_ADCxADCx Module GCLK max input freq——100MHz
ADC Single-Ended Throughput Rates
ADC25FTP (Single-Ended Mode)Throughput Rate (3) (Single-Ended)12.31—1231ksps12-bit resolution, Rsource ≤147 Ω, SAMPCTRL.SAMPLEN=0 (1)
13.33—133310-bit resolution, Rsource ≤147 Ω, SAMPCTRL.SAMPLEN=0 (1)
16—16008-bit resolution, Rsource ≤147 Ω, SAMPCTRL.SAMPLEN=0 (1)
10—1000ksps12-bit resolution, Rsource ≤6,550Ω SAMPCTRL.SAMPLEN=n/a (2)
10.67—106710-bit resolution, Rsource ≤6,550 Ω SAMPCTRL.SAMPLEN=n/a (2)
12.31—12318-bit resolution, Rsource ≤6,550 Ω SAMPCTRL.SAMPLEN=n/a (2)
ADC Differential Mode Throughput Rates
ADC27FTP (Differential Mode) Throughput Rate (3) (Differential Mode)12.31—1231ksps12-bit resolution, Rsource ≤147 Ω, SAMPCTRL.SAMPLEN=0 (1)
14.55—145510-bit resolution, Rsource ≤147 Ω, SAMPCTRL.SAMPLEN=0 (1)
17.78—17788-bit resolution, Rsource ≤147 Ω, SAMPCTRL.SAMPLEN=0 (1)
10—1000ksps12-bit resolution, Rsource ≤6,550Ω SAMPCTRL.SAMPLEN=n/a (2)
11.43—114310-bit resolution, Rsource ≤6,550 Ω SAMPCTRL.SAMPLEN=n/a (2)
13.33—13338-bit resolution, Rsource ≤6,550 Ω SAMPCTRL.SAMPLEN=n/a (2)
Note:
  1. ADC_ Sample time = ((SAMPCTRL.SAMPLEN + 1) * TAD) and SAMPCTRL.OFFCOMP=0.
  2. ADC_ HDW forces sample time to 4*TAD when SAMPCTRL.OFFCOMP=1, user SAMPCTRL.SAMPLEN is ignored.
  3. ADC Throughput Rate FTP = ((1 / ((TSAMP + TCNV) * TAD)) / (# of user active analog inputs in use on specific target ADC module)). # of active analog channels used =1.
  4. These values are based on simulation, and not covered by production test limits or characterization.
Table 54-24. ADC Sample Timing Requirements (4)
AC CHARACTERISTICSStandard Operating Conditions: VDDIO=VDDANA 1.71V to 3.63V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Param. No.SymbolCharacteristicsMin.TypicalMax.UnitsConditions
ADC29TSAMPADC Sample Time (1,2,3)1(1)——TADTAD(min) Ext Analog Input Rsource ≤ 147 Ω
2(1)——TAD(min) , Ext Analog Input Rsource ≤ 2,250 Ω
3(1)——TAD(min) , Ext Analog Input Rsource ≤ 4,400 Ω
4(1,2)——TAD(min), Ext Analog Input Rsource ≤ 6,550 Ω
5(1)——TAD(min) , Ext Analog Input Rsource ≤ 8,700 Ω
6(1)——TAD(min) , Ext Analog Input Rsource ≤ 10,850 Ω
See Note 5nsSample time with DAC as input
10000——Sample time with Temp sensor or band gap as input
ADC31TCNVConversion Time (3) (Single-Ended Mode)12TAD12-bit resolution
1110-bit resolution
98-bit resolution
ADC33Conversion Time (3) (Differential Mode)1212-bit resolution
1010-bit resolution
88-bit resolution
ADC35CSAMPLEADC Internal Sample Cap2—3pf
ADC37RSAMPLEADC Internal impedance——2000Ω
Note:
  1. When SAMPCTRL.OFFCOMP = 0:
    • TSAMP = (((RSAMPLE + RSOURCE) * CSAMPLE * 9.7) / TAD)+1 rounded down to nearest whole integer
    • User SAMPCTRL.SAMPLEN = (TSAMP - 1)
  2. When SAMPCTRL.OFFCOMP=1:
    • TSAMP = 4 (Forced by HDW)
    • User SAMPCTRL.SAMPLEN = (n/a, Ignored by HDW)
  3. ADC Throughput Rate FTP = ((1 / ((TSAMP + TCNV) * TAD)) / (# of user active analog inputs in use on specific target ADC module)).
  4. These values are based on simulation and are not covered by production test limits or characterization.
  5. See ts specified in DAC Electrical Characteristics.
Table 54-25. Differential Mode ADC Electrical Specifications (1)
AC CHARACTERISTICSStandard Operating Conditions: VDDIO=VDDANA 1.71V to 3.63V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param. No.SymbolCharacteristicsMin.TypicalMax.UnitsConditions
DIFFERENTIAL MODE ADC Accuracy
DADC41ResResolution8—12bitsSelectable 8, 10, 12 bit Resolution Ranges
DADC43EN0B Effective Number of bits10.5——1msps, R2R disabled, VREF = VDDANA = VDDIO = 3.0
DADC4510.5——1msps, R2R disabled, External VREF = 2.0V, VDDANA = VDDIO = 3.0
DADC47INL Integral Nonlinearity-1.5—+1.5LSb1msps, R2R disabled, VREF = VDDANA = VDDIO = 3.0
DADC49-1.5—+1.51msps, R2R disabled, External VREF = 2.0V, VDDANA = VDDIO = 3.0
DADC51DNL Differential Nonlinearity-1.0—+1.01msps, R2R disabled,VREF = VDDANA = VDDIO = 3.0
DADC53-1.0—+1.01msps, R2R disabled, External VREF = 2.0V, VDDANA = VDDIO = 3.0
DADC55GERRGain Error with REFCTRL.REFCOMP=1- 0.18—+0.16%FSR1msps, VREF = VDDANA = VDDIO = 3.0
DADC57- 0.09—+0.181msps, External VREF = 2.0V, VDDANA = VDDIO = 3.0
DADC59- 4.3—+1.81msps, VREF=1V Internal band gap, VDDANA = VDDIO = 3.0
DADC61- 0.35—+0.651msps, VREF = VDDANA/2, VDDANA = VDDIO = 3.0
DADC63Gain Error with REFCTRL.REFCOMP=0- 0.2—+0.161msps, VREF = VDDANA = VDDIO = 3.0
DADC65- 0.74—+0.661msps, External VREF = 2.0V, VDDANA = VDDIO = 3.0
DADC67- 4.9—+1.61msps, VREF=1V Internal band gap, VDDANA = VDDIO = 3.0
DADC69- 1—+1.01msps, VREF = VDDANA/2, VDDANA = VDDIO = 3.0
DADC71E0FFOffset Error with SAMPCTRL.OFFCOMP=1- 2.9—+2.4mV1msps, Internal VREF = VDDANA = VDDIO = 3.0
DADC73- 2.6—+2.11msps, External VREF = 2.0V, VDDANA = VDDIO = 3.0
DADC75- 2.3—+2.31msps, VREF=1V Internal band gap, VDDANA = VDDIO = 3.0
DADC77- 2.9—+2.61msps, VREF = VDDANA/2, VDDANA = VDDIO = 3.0
DADC79Offset Error with SAMPCTRL.OFFCOMP=0- 9.5—+9.91msps, VREF = VDDANA = VDDIO = 3.0
DADC81- 9.9—+9.81msps, External VREF = 2.0V, VDDANA = VDDIO = 3.0
DADC83- 5.0—+5.01msps, VREF=1V Internal band gap, VDDANA = VDDIO = 3.0
DADC85- 10.8—+11.31msps, VREF = VDDANA/2, VDDANA = VDDIO = 3.0
DADC87TUE(3)Total Unadjusted Error-5.2—+5.2LSb1msps, R2R disabled, Internal VREF = VDDANA = VDDIO = 3.0
DADC89-5.6—+5.61msps, R2R disabled, External VREF = 2.0V, VDDANA = VDDIO = 3.0
DIFFERENTIAL MODE ADC Dynamic Performance
DADC91SINAD Signal to Noise and Distortion65.3——dBVREF=VDDANA=VDDIO=3.0v @ 12bit max sampling rate, Fin = 14 kHz / Full range Input signal (2)
DADC93SNR Signal to Noise ratio64.7——
DADC95SFDR Spurious Free Dynamic Range76.6——
DADC97THD Total Harmonic Distortion——-78.6
DADC99NrmsNoise RMS——2.4mVExternal VREF = 2.0V, VDDANA = VDDIO = 3.0, Constant Input Voltage
2.5VREF = VDDANA = VDDIO = 3.0, Constant Input Voltage
Note:
  1. These values are based on characterization. These values are not covered by test limits in production.
  2. All values expressed in decibel refer to the full scale input and are tested with an input signal 0.35dB below full scale; THD measured on the first seven harmonics of the input signal.
  3. With REFCTRL.REFCOMP=1 and SAMPCTRL.OFFCOMP=1.
Table 54-26. Single Ended Mode ADC Electrical Specifications (1)
AC CHARACTERISTICSStandard Operating Conditions: VDDIO=VDDANA 1.71V to 3.63V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param. No.SymbolCharacteristicsMin.TypicalMax.UnitsConditions
SINGLE ENDED MODE ADC Accuracy
SADC41ResResolution8—12bitsSelectable 8, 10, 12 bit Resolution Ranges
SADC43EN0B Effective Number of bits8.9——1msps, R2R disabled, VREF = VDDANA = VDDIO = 3.0
SADC458.9——1msps, R2R disabled, External VREF = 2.0V, VDDANA = VDDIO = 3.0
SADC47INL Integral Nonlinearity-3.2—+3.2LSb1msps, R2R disabled, VREF = VDDANA = VDDIO = 3.0
SADC49-3.0—+3.01msps, R2R disabled, External VREF = 2.0V, VDDANA = VDDIO = 3.0
SADC51DNL Differential Nonlinearity-1.0—+1.01msps, R2R disabled,VREF = VDDANA = VDDIO = 3.0
SADC53-1.0—+1.11msps, R2R disabled, External VREF = 2.0V, VDDANA = VDDIO = 3.0
SADC55GERRGain Error with REFCTRL.REFCOMP=1- 0.30—+0.30%FSR1msps, VREF = VDDANA = VDDIO = 3.0
SADC57- 0.20—+0.251msps, External VREF = 2.0V, VDDANA = VDDIO = 3.0
SADC59- 4.2—+1.81msps, VREF=1V Internal band gap, VDDANA = VDDIO = 3.0
SADC61- 0.4—+0.61msps, VREF = VDDANA/2, VDDANA = VDDIO = 3.0
SADC71E0FFOffset Error with SAMPCTRL.OFFCOMP=1- 18—+7mV1msps, Internal VREF = VDDANA = VDDIO = 3.0
SADC73- 18.6—+131msps, External VREF = 2.0V, VDDANA = VDDIO = 3.0
SADC75- 24—+191msps, VREF=1V Internal band gap, VDDANA = VDDIO = 3.0
SADC77- 22—+241msps, VREF = VDDANA/2, VDDANA = VDDIO = 3.0
SADC87TUE(3)Total Unadjusted Error-18.3—+18.3LSb1msps, R2R disabled, Internal VREF = VDDANA = VDDIO = 3.0
SADC89-19.1—+19.11msps, R2R disabled, External VREF = 2.0V, VDDANA = VDDIO = 3.0
SINGLE ENDED MODE ADC Dynamic Performance
SADC91SINAD Signal to Noise and Distortion55.7——dBVREF=VDDANA=VDDIO=3.0v @ 12bit max sampling rate, Fin = 14 kHz / Full range Input signal (2)
SADC93SNR Signal to Noise ratio54.7——
SADC95SFDR Spurious Free Dynamic Range67.9——
SADC97THD Total Harmonic Distortion——-65.8
SADC99NrmsNoise RMS——2.1mVExternal VREF = 2.0V, VDDANA = VDDIO = 3.0, Constant Input Voltage
1.7VREF = VDDANA = VDDIO = 3.0, Constant Input Voltage
Note:
  1. These values are based on characterization. These values are not covered by test limits in production.
  2. All values expressed in decibel refer to the full scale input and are tested with an input signal 0.35dB below full scale; THD measured on the first seven harmonics of the input signal.
  3. With REFCTRL.REFCOMP=1 and SAMPCTRL.OFFCOMP=1.
Table 54-27. Power Consumption
SymbolParametersConditionsTATyp.MaxUnits
IDD VDDANADifferential modefs = 1 Msps / Reference buffer disabled / VDDANA = VREF = 3.0VMax 85°C Typ 25°C279318 µA
fs = 1 Msps / Reference buffer enabled / VDDANA = 3.0V, VREF = 2.0V482653
fs = 10 ksps / Reference buffer disabled / VDDANA = VREF = 3.0V2845
fs = 10 ksps / Reference buffer enabled / VDDANA = 3.0V, VREF = 2.0V241397
Single Ended modefs = 1 Msps / Reference buffer disabled / VDDANA = VREF = 3.0VMax 85°C Typ 25°C307348 µA
fs = 1 Msps / Reference buffer enabled / VDDANA = 3.0V, VREF = 2.0V499 681
fs = 10 ksps / Reference buffer disabled / VDDANA = VREF = 3.0V38 60
fs = 10 ksps / Reference buffer enabled / VDDANA = 3.0V, VREF = 2.0V245400