18.6.3.3 Sleep Mode Controller

A Sleep mode is entered by executing the Wait For Interrupt instruction (WFI). The Sleep Mode bits in the Sleep Configuration register (SLEEPCFG.SLEEPMODE) select the level of the sleep mode.

Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG.SLEEPCFG register due to bridges. Software must ensure that the SLEEPCFG register reads the desired value before executing a WFI instruction.

Note: After power-up, the MAINVREG low power mode takes some time to stabilize. Once stabilized, the INTFLAG.SLEEPRDY bit is set. Before entering Standby, Hibernate or Backup mode, software must ensure that the INTFLAG.SLEEPRDY bit is set.

Table 18-1. Sleep Mode Entry and Exit Table
Mode	Mode Entry	Wake-Up Sources
IDLE	SLEEPCFG.SLEEPMODE = IDLE	Synchronous ⁽²⁾ (APB, AHB), asynchronous ⁽¹⁾
STANDBY	SLEEPCFG.SLEEPMODE = STANDBY	Synchronous ⁽³⁾, asynchronous ⁽¹⁾
HIBERNATE	SLEEPCFG.SLEEPMODE = HIBERNATE	Hibernate reset detected by the RSTC
BACKUP	SLEEPCFG.SLEEPMODE = BACKUP	Backup reset detected by the RSTC
OFF	SLEEPCFG.SLEEPMODE = OFF	External Reset

Note:

Asynchronous: interrupt generated on generic clock, external clock, or external event.
Synchronous: interrupt generated on synchronous (APB or AHB) clock.
Synchronous interrupt only for peripherals configured to run in standby.

Note: The type of wake-up sources (synchronous or asynchronous) is given in each module interrupt section.

The sleep modes (idle, standby, hibernate, backup, and off) and their effect on the clocks activity, the regulator and the NVM state are described in the table and the sections below. Refer to Power Domain Controller for the power domain gating effect.

Table 18-2. Sleep Mode Overview
Mode	Main clock	CPU	AHBx and APBx clock	GCLK clocks	Oscillators		Regulator	NVM
Mode	Main clock	CPU	AHBx and APBx clock	GCLK clocks	ONDEMAND = 0	ONDEMAND = 1	Regulator	NVM
Active	Run	Run	Run	Run⁽¹⁾	Run	Run if requested	MAINVREG	active
IDLE	Run	Stop	Stop⁽²⁾	Run⁽¹⁾	Run	Run if requested	MAINVREG	active
STANDBY	Stop	Stop	Stop⁽²⁾	Stop⁽²⁾	Run if requested or RUNSTDBY=1	Run if requested	MAINVREG in low power mode	Ultra Low power
HIBERNATE	Stop	Stop	Stop	Stop	Stop	Stop	MAINVREG in low power mode	Ultra Low power+
BACKUP	Stop	Stop	Stop	Stop	Stop	Stop	Backup regulator (LPVREG)	OFF
OFF	Stop	Stop	Stop	OFF	OFF	OFF	OFF	OFF

Note:

Running if requested by peripheral during SleepWalking
Running during SleepWalking