51.9.2 Clock Unit n Control
| Name: | CLKCTRLn |
| Offset: | 0x04 + n*0x04 [n=0..1] |
| Reset: | 0x00000000 |
| Property: | Enable-Protected, PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MCKOUTDIV[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MCKDIV[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MCKOUTINV | MCKEN | MCKSEL | SCKOUTINV | SCKSEL | FSOUTINV | FSINV | FSSEL | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BITDELAY | FSWIDTH[1:0] | NBSLOTS[2:0] | SLOTSIZE[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 29:24 – MCKOUTDIV[5:0] Host Clock Output Division Factor
The generic clock selected by MCKSEL is divided by (MCKOUTDIV + 1) to obtain the Host Clock n output.
Bits 21:16 – MCKDIV[5:0] Host Clock Division Factor
The Host Clock n is divided by (MCKDIV + 1) to obtain the Serial Clock n.
Bit 15 – MCKOUTINV Host Clock Output Invert
| Value | Description |
|---|---|
| 0 | The Host Clock n is output without inversion. |
| 1 | The Host Clock n is inverted before being output. |
Bit 14 – MCKEN Host Clock Enable
| Value | Description |
|---|---|
| 0 | The Host Clock n division and output is disabled. |
| 1 | The Host Clock n division and output is enabled. |
Bit 13 – MCKSEL Host Clock Select
This field selects the source of the Host Clock n.
| MCKSEL | Name | Description |
|---|---|---|
| 0x0 | GCLK | GCLK_I2S_n is used as Host Clock n source |
| 0x1 | MCKPIN | MCKn input pin is used as Host Clock n source |
Bit 12 – SCKOUTINV Serial Clock Output Invert
| Value | Description |
|---|---|
| 0 | The Serial Clock n is output without inversion. |
| 1 | The Serial Clock n is inverted before being output. |
Bit 11 – SCKSEL Serial Clock Select
This field selects the source of the Serial Clock n.
| SCKSEL | Name | Description |
|---|---|---|
| 0x0 | MCKDIV | Divided Host Clock n is used as Serial Clock n source |
| 0x1 | SCKPIN | SCKn input pin is used as Serial Clock n source |
Bit 10 – FSOUTINV Frame Sync Output Invert
| Value | Description |
|---|---|
| 0 | The Frame Sync n is output without inversion. |
| 1 | The Frame Sync n is inverted before being output. |
Bit 9 – FSINV Frame Sync Invert
| Value | Description |
|---|---|
| 0 | The Frame Sync n is used without inversion. |
| 1 | The Frame Sync n is inverted before being used. |
Bit 8 – FSSEL Frame Sync Select
This field selects the source of the Frame Sync n.
| FSSEL | Name | Description |
|---|---|---|
| 0x0 | SCKDIV | Divided Serial Clock n is used as Frame Sync n source |
| 0x1 | FSPIN | FSn input pin is used as Frame Sync n source |
Bit 7 – BITDELAY Data Delay from Frame Sync
| BITDELAY | Name | Description |
|---|---|---|
| 0x0 | LJ | Left Justified (0 Bit Delay) |
| 0x1 | I2S | I2S (1 Bit Delay) |
Bits 6:5 – FSWIDTH[1:0] Frame Sync Width
This field selects the duration of the Frame Sync output pulses.
When not in Burst mode, the Clock unit n operates in continuous mode when enabled, with periodic Frame Sync pulses and Data samples.
In Burst mode, a single Data transfer starts at each Frame Sync pulse; these pulses are 1-bit wide and occur only when a Data transfer is requested.
| FSWIDTH[1:0] | Name | Description |
|---|---|---|
| 0x0 | SLOT | Frame Sync Pulse is 1 Slot wide (default for I2S protocol) |
| 0x1 | HALF | Frame Sync Pulse is half a Frame wide |
| 0x2 | BIT | Frame Sync Pulse is 1 Bit wide |
| 0x3 | BURST | Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested |
Bits 4:2 – NBSLOTS[2:0] Number of Slots in Frame
Each Frame for Clock Unit n is composed of (NBSLOTS + 1) Slots.
Bits 1:0 – SLOTSIZE[1:0] Slot Size
Each Slot for Clock Unit n is composed of a number of bits specified by SLOTSIZE.
| SLOTSIZE[1:0] | Name | Description |
|---|---|---|
| 0x0 | 8 | 8-bit Slot for Clock Unit n |
| 0x1 | 16 | 16-bit Slot for Clock Unit n |
| 0x2 | 24 | 24-bit Slot for Clock Unit n |
| 0x3 | 32 | 32-bit Slot for Clock Unit n |