54.14.3 QSPI Characteristics
Name | Description | Mode | VDD = 1.8V | VDD = 3.3V | Units | ||||
---|---|---|---|---|---|---|---|---|---|
Min. | Typ. | Max. | Min. | Typ. | Max. | ||||
fSDR_m0_m2 | QSPI SDR Frequency | Host SDR Mode 0/2 | - | - | 50.0 | - | - | 75 | MHz |
fSDR_m1_m3 | QSPI SDR Frequency | Host SDR Mode 1/3 | - | - | 50.0 | - | - | 50 | |
fDDR | QSPI DDR Frequency | Host mode | - | - | 37.5 | - | - | 66 | |
tSDR_QSPI0 | Input Setup Time | Host SDR mode 0 | 3.86 | - | - | 3.85 | - | - | ns |
tSDR_QSPI1 | Input Hold Time | Host SDR mode 0 | 0.00 | - | - | 0.19 | - | - | |
tSDR_QSPI2 | Data Out Valid Time | Host SDR mode 0 | - | - | 3.33 | - | - | 2.67 | |
tSDR_QSPI3 | Input Setup Time | Host SDR mode 1 | 3.79 | - | - | 3.59 | - | - | ns |
tSDR_QSPI4 | Input Hold Time | Host SDR mode 1 | 0.06 | - | - | 0.19 | - | - | |
tSDR_QSPI5 | Data Out Valid Time | Host SDR mode 1 | - | - | 2.71 | - | - | 2.71 | |
tSDR_QSPI6 | Input Setup Time | Host SDR mode 2 | 3.79 | - | - | 3.58 | - | - | ns |
tSDR_QSPI7 | Input Hold Time | Host SDR mode 2 | 0.06 | - | - | 0.19 | - | - | |
tSDR_QSPI8 | Data Out Valid Time | Host SDR mode 2 | - | - | 2.74 | - | - | 2.65 | |
tSDR_QSPI9 | Input Setup Time | Host SDR mode 3 | 3.86 | - | - | 3.86 | - | - | ns |
tSDR_QSPI10 | Input Hold Time | Host SDR mode 3 | -0.10 | - | - | 0.19 | - | - | |
tSDR_QSPI11 | Data Out Valid Time | Host SDR mode 3 | - | - | 3.22 | - | - | 2.60 | |
tDDR_QSPI0f | Input Setup Time | Host DDR mode 0 fall edge | 3.87 | - | - | 3.85 | - | - | ns |
tDDR_QSPI1f | Input Hold Time | Host DDR mode 0 fall edge | 0.00 | - | - | 0.19 | - | - | |
tDDR_QSPI2f | Data Out Valid Time | Host DDR mode 0 fall edge | - | - | 2.1 | - | - | 2.03 | |
tDDR_QSPI0r | Input Setup Time | Host DDR mode 0 rise edge | 3.81 | - | - | 3.57 | - | - | |
tDDR_QSPI1r | Input Hold Time | Host DDR mode 0 rise edge | 0.06 | - | - | 0.19 | - | - | |
tDDR_QSPI2r | Data Out Valid Time | Host DDR mode 0 rise edge | - | - | 3.13 | - | - | 2.12 |
Note:
- These values are based on simulation. They are not covered by production test limits or characterization.
- All timing characteristics are given for 20pF capacitive load.
QSPI Mode | CLK_QSPI2X _AHB | CLK_QSPI _AHB | Max. CPU_CLK | Max. QSPI Speed | Conditions |
---|---|---|---|---|---|
SDR | X | 120 MHz | 120 MHz | 60 MHz(2) | BAUD -> BAUD[7:0] must be greater than 0 to ensure QSPI clock frequency is as per electrical specifications provided in table 54-57. |
X | 75 MHz | 75 MHz | 75 MHz | - | |
DDR | 132 MHz | 66 MHz | 66 MHz | 66 MHz | - |
Note:
- Examples shown do not supersede the electrical specifications shown in Table 54-57. QSPI Timing Characteristics.
- CPU clock frequency(CPU_CLK) should always be multiple of SQI frequency (CLK_QSPI_AHB).