54.6 Maximum Clock Frequencies
| Symbol | Description | Conditions | Fmax | Units |
|---|---|---|---|---|
| fGCLKGEN0 / fGCLK_MAIN (see Note 2) | GCLK Generator Output Frequency | undivided | 200 | MHz |
| FgclkgenX, x={1;7} | 200 | MHz | ||
| FgclkgenX, , x={8;11} | 100 | MHz |
Note:
- These values are based on simulation. They are not covered by production test limits or characterization.
- GCLK Generator 0 output frequency must not exceed the AHB clock frequency. The output must be divided in case of the GCLK Generator 0 input frequency is higher than the AHB clock frequency.
| Symbol | Description | Max. | Units |
|---|---|---|---|
| fCPU | CPU clock frequency | 120 | MHz |
| fAHB | AHB clock frequency | 120 | MHz |
| fAPBx, x = {A, B, C, D} | APBA, APBB, APBC and APBD clock frequency | 120 | MHz |
| fGCLK_DPLLx, x = {0,1} | FDPLL0 and FDPLL1 Reference clock frequency | 3.2 | MHz |
| fGCLK_DPLLx_32K, x = {0,1} | FDPLL0 and FDPLL1 32k Reference clock frequency | 100 | kHz |
| fGCLK_DFLL48M_REF | DFLL48M Reference clock frequency | 33 | kHz |
| fGCLK_EIC | EIC input clock frequency | 100 | MHz |
| fGCLK_FREQM_MSR | FREQM Measure | 200 | MHz |
| fGCLK_FREQM_REF | FREQM Reference | 100 | MHz |
| fGCLK_EVSYS_CHANNEL_x, x = {0,.., 11} | EVSYS channel x input clock frequency | 100 | MHz |
| fGCLK_SERCOMx_SLOW, x = {0, ... , 7} | Common SERCOMx slow input clock frequency | 12 | MHz |
| fGCLK_SERCOMx_CORE, x = {0, ... , 7} | SERCOMx input clock frequency | 100 | MHz |
| fGCLK_CANx, x = {0, 1} | CANx input clock frequency | 100 | MHz |
| fGCLK_USB | USB input clock frequency | 60 | MHz |
| fGCLK_I2S | I2S input clock frequency | 100 | MHz |
| fGCLK_SDHCx_SLOW, x = {0, 1} | Common SDHCx slow input clock frequency | 12 | MHz |
| fGCLK_SDHCx_CORE, x = {0, 1} | SDHCx input clock frequency | 150 | MHz |
| fGCLK_TCCx, x = {0, ... , 4} | TCCx input clock frequency | 200 | MHz |
| fGCLK_TCx, x = {0, ... , 3} | TC0, TC1, TC2, TC3 input clock frequency | 200 | MHz |
| fGCLK_TCx, x = {4, ... , 7} | TC4, TC5, TC6, TC7 input clock frequency | 100 | MHz |
| fGCLK_PDEC | PDEC input clock frequency | 200 | MHz |
| fGCLK_CCL | CCL input clock frequency | 100 | MHz |
| fGCLK_GCLKIN | External GCLK input clock frequency | 50 | MHz |
| fGCLK_CM4_TRACE | CM4 Trace input clock frequency | 120 | MHz |
| fGCLK_AC | AC digital input clock frequency | 100 | MHz |
| fGCLK_ADCx, x = {0, 1} | ADCx input clock frequency | 100 | MHz |
| fGCLK_DAC | DAC input clock frequency | 100 | MHz |
Note:
- These values are based on simulation. They are not covered by production test limits or characterization.