2.6 Timer1

In Asynchronous External Counter mode, TCS bit (T1CON[1] = 1), TSYNC bit (T1CON[2] = 0) and TECS[1:0] (T1CON[9:8] = ‘0b01)), the Timer1 register (TMR1) does not reflect the first count from an external T1CLK input.

Work Around

Always add 1 to the Timer1 count value to reflect the first count from an external T1CLK input.

Affected Silicon Revisions


A0	A1	B0	C0
X	X	X	X

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