1 Ethernet Driver Library
1.1 Introduction
The Ethernet Driver library for MCC Melody provides drivers for the ENC28J60 and ENCX24J600 family of controllers. It allows for quick and easy configuration and code generation for applications using SPI in polling mode.
1.2 Supported Device Families
| PIC16F | PIC18F | tiny AVR | AVR |
1.3 Required Header Files:
#include "mcc_generated_files/ethernet/physical_layer_interface.h"
1.4 Module Documentation
1.4.1 ENC28J60
This header file provides API prototypes and other data types for the ENC28J60 Ethernet Driver.
1.4.1.1 Module description
This header file provides API prototypes and other data types for the ENC28J60 Ethernet Driver.
1.4.1.1.1 Data structures
union eir_t
ENC28J60 EIR register.
union phstat2_t
ENC28J60 PHSTAT2 register.
union receiveStatusVector_t
ENC28J60 receive status vector.
1.4.1.1.2 Definitions
#define ETH_NCS_HIGH() do{ETH_CS_SetHigh();} while(0)
Sets Ethernet Chip Select to high.
#define ETH_NCS_LOW() do{ETH_CS_SetLow();} while(0)
Sets Ethernet Chip Select to low.
#define ETH_SPI_READ8() SPI1_Host.ByteExchange(0)
Reads the SPI byte.
#define ETH_SPI_WRITE8(a) SPI1_Host.ByteExchange(a)
Writes the SPI byte.
#define ETH_WRITE_IN_PROGRESS (0x0001 << 0)
Packet write in progress, not ready for transmit.
#define ETH_TX_QUEUED (0x0001 << 1)
Packet complete, in queue for transmit.
#define ETH_ALLOCATED (0x0001 << 2)
Flag for pool management. Set to either free or allocated.
1.4.1.1.3 Enumerations
enum spi_inst_t { rcr_inst = 0x00, rbm_inst = 0x3A, wcr_inst = 0x40, wbm_inst = 0x7A, bfs_inst = 0x80, bfc_inst = 0xa0, src_inst = 0xFF }
SPI instructions.
enum sfr_bank_t { sfr_bank0 = SFR_BANK0, sfr_bank1 = SFR_BANK1, sfr_bank2 = SFR_BANK2, sfr_bank3 = SFR_BANK3, sfr_common = SFR_COMMON, sfr_bank0 = SFR_BANK0, sfr_bank1 = SFR_BANK1, sfr_bank2 = SFR_BANK2, sfr_bank3 = SFR_BANK3, sfr_common = SFR_COMMON }
SFR banks.
enum enc28j60_registers_t { J60_ERDPTL = (SFR_BANK0 | 0x00), J60_ERDPTH = (SFR_BANK0 | 0x01), J60_EWRPTL = (SFR_BANK0 | 0x02), J60_EWRPTH = (SFR_BANK0 | 0x03), J60_ETXSTL = (SFR_BANK0 | 0x04), J60_ETXSTH = (SFR_BANK0 | 0x05), J60_ETXNDL = (SFR_BANK0 | 0x06), J60_ETXNDH = (SFR_BANK0 | 0x07), J60_ERXSTL = (SFR_BANK0 | 0x08), J60_ERXSTH = (SFR_BANK0 | 0x09), J60_ERXNDL = (SFR_BANK0 | 0x0A), J60_ERXNDH = (SFR_BANK0 | 0x0B), J60_ERXRDPTL = (SFR_BANK0 | 0x0C), J60_ERXRDPTH = (SFR_BANK0 | 0x0D), J60_ERXWRPTL = (SFR_BANK0 | 0x0E), J60_ERXWRPTH = (SFR_BANK0 | 0x0F), J60_EDMASTL = (SFR_BANK0 | 0x10), J60_EDMASTH = (SFR_BANK0 | 0x11), J60_EDMANDL = (SFR_BANK0 | 0x12), J60_EDMANDH = (SFR_BANK0 | 0x13), J60_EDMADSTL = (SFR_BANK0 | 0x14), J60_EDMADSTH = (SFR_BANK0 | 0x15), J60_EDMACSL = (SFR_BANK0 | 0x16), J60_EDMACSH = (SFR_BANK0 | 0x17), RSRV_018 = (SFR_BANK0 | 0x18), RSRV_019 = (SFR_BANK0 | 0x19), RSRV_01A = (SFR_BANK0 | 0x1A), J60_EHT0 = (SFR_BANK1 | 0x00), J60_EHT1 = (SFR_BANK1 | 0x01), J60_EHT2 = (SFR_BANK1 | 0x02), J60_EHT3 = (SFR_BANK1 | 0x03), J60_EHT4 = (SFR_BANK1 | 0x04), J60_EHT5 = (SFR_BANK1 | 0x05), J60_EHT6 = (SFR_BANK1 | 0x06), J60_EHT7 = (SFR_BANK1 | 0x07), J60_EPMM0 = (SFR_BANK1 | 0x08), J60_EPMM1 = (SFR_BANK1 | 0x09), J60_EPMM2 = (SFR_BANK1 | 0x0A), J60_EPMM3 = (SFR_BANK1 | 0x0B), J60_EPMM4 = (SFR_BANK1 | 0x0C), J60_EPMM5 = (SFR_BANK1 | 0x0D), J60_EPMM6 = (SFR_BANK1 | 0x0E), J60_EPMM7 = (SFR_BANK1 | 0x0F), J60_EPMCSL = (SFR_BANK1 | 0x10), J60_EPMCSH = (SFR_BANK1 | 0x11), RSRV_112 = (SFR_BANK1 | 0x12), RSRV_113 = (SFR_BANK1 | 0x13), J60_EPMOL = (SFR_BANK1 | 0x14), J60_EPMOH = (SFR_BANK1 | 0x15), RSRV_116 = (SFR_BANK1 | 0x16), RSRV_117 = (SFR_BANK1 | 0x17), J60_ERXFCON = (SFR_BANK1 | 0x18), J60_EPKTCNT = (SFR_BANK1 | 0x19), RSRV_11A = (SFR_BANK1 | 0x1A), J60_MACON1 = (SFR_BANK2 | 0x00), RSRV_201 = (SFR_BANK2 | 0x01), J60_MACON3 = (SFR_BANK2 | 0x02), J60_MACON4 = (SFR_BANK2 | 0x03), J60_MABBIPG = (SFR_BANK2 | 0x04), RSRV_205 = (SFR_BANK2 | 0x05), J60_MAIPGL = (SFR_BANK2 | 0x06), J60_MAIPGH = (SFR_BANK2 | 0x07), J60_MACLCON1 = (SFR_BANK2 | 0x08), J60_MACLCON2 = (SFR_BANK2 | 0x09), J60_MAMXFLL = (SFR_BANK2 | 0x0A), J60_MAMXFLH = (SFR_BANK2 | 0x0B), RSRV_20C = (SFR_BANK2 | 0x0C), RSRV_20D = (SFR_BANK2 | 0x0D), RSRV_20E = (SFR_BANK2 | 0x0E), RSRV_20F = (SFR_BANK2 | 0x0F), RSRV_210 = (SFR_BANK2 | 0x10), RSRV_211 = (SFR_BANK2 | 0x11), J60_MICMD = (SFR_BANK2 | 0x12), RSRV_213 = (SFR_BANK2 | 0x13), J60_MIREGADR = (SFR_BANK2 | 0x14), RSRV_215 = (SFR_BANK2 | 0x15), J60_MIWRL = (SFR_BANK2 | 0x16), J60_MIWRH = (SFR_BANK2 | 0x17), J60_MIRDL = (SFR_BANK2 | 0x18), J60_MIRDH = (SFR_BANK2 | 0x19), RSRV_21A = (SFR_BANK2 | 0x1A), J60_MAADR5 = (SFR_BANK3 | 0x00), J60_MAADR6 = (SFR_BANK3 | 0x01), J60_MAADR3 = (SFR_BANK3 | 0x02), J60_MAADR4 = (SFR_BANK3 | 0x03), J60_MAADR1 = (SFR_BANK3 | 0x04), J60_MAADR2 = (SFR_BANK3 | 0x05), J60_EBSTSD = (SFR_BANK3 | 0x06), J60_EBSTCON = (SFR_BANK3 | 0x07), J60_EBSTCSL = (SFR_BANK3 | 0x08), J60_EBSTCSH = (SFR_BANK3 | 0x09), J60_MISTAT = (SFR_BANK3 | 0x0A), RSRV_30B = (SFR_BANK3 | 0x0B), RSRV_30C = (SFR_BANK3 | 0x0C), RSRV_30D = (SFR_BANK3 | 0x0D), RSRV_30E = (SFR_BANK3 | 0x0E), RSRV_30F = (SFR_BANK3 | 0x0F), RSRV_310 = (SFR_BANK3 | 0x10), RSRV_311 = (SFR_BANK3 | 0x11), J60_EREVID = (SFR_BANK3 | 0x12), RSRV_313 = (SFR_BANK3 | 0x13), RSRV_314 = (SFR_BANK3 | 0x14), J60_ECOCON = (SFR_BANK3 | 0x15), RSRV_316 = (SFR_BANK3 | 0x16), J60_EFLOCON = (SFR_BANK3 | 0x17), J60_EPAUSL = (SFR_BANK3 | 0x18), J60_EPAUSH = (SFR_BANK3 | 0x19), RSRV_31A = (SFR_BANK3 | 0x1A), J60_EIE = (SFR_COMMON | 0x1B), J60_EIR = (SFR_COMMON | 0x1C), J60_ESTAT = (SFR_COMMON | 0x1D), J60_ECON2 = (SFR_COMMON | 0x1E), J60_ECON1 = (SFR_COMMON | 0x1F) }
ENC28J60 registers.
enum enc28j60_phy_registers_t { J60_PHCON1 = 0x00, J60_PHSTAT1 = 0x01, J60_PHID1 = 0x02, J60_PHID2 = 0x03, J60_PHCON2 = 0x10, J60_PHSTAT2 = 0x11, J60_PHIE = 0x12, J60_PHIR = 0x13, J60_PHLCON = 0x14 }
ENC28J60 PHY register addresses.
1.4.1.1.4 Functions
phy_error_msg ETH_SendQueued (void)
Enqueues the latest written packet and starts the transmission of a queued packet.
phy_error_msg ETH_Shift_Tx_Packets (void)
Copies the queued packets to the TX Buffer start address using the DMA setup.
void ETH_PacketListReset (void)
Resets the Ethernet packet list.
txPacket_t * ETH_NewPacket (void)
Allocates a new packet element and links it to the chained list.
void ETH_RemovePacket (txPacket_t *pPacket)
Deallocates a packet element and unlinks it from the chained list.
static uint16_t ETH_ComputeChecksum (uint16_t len, uint16_t seed)
Calculates the checksum.
static uint8_t ENC28_Rcr8 (enc28j60_registers_t a)
Reads one byte from Special Function Register (SFR).
static uint16_t ENC28_Rcr16 (enc28j60_registers_t a)
Reads two bytes from SFRs.
static void ENC28_Wcr8 (enc28j60_registers_t a, uint8_t v)
Writes one byte to SFRs.
static void ENC28_Wcr16 (enc28j60_registers_t a, uint16_t v)
Writes two bytes to SFRs.
static void ENC28_Bfs (enc28j60_registers_t a, char bits)
Sets the SFR bit field.
static void ENC28_Bfc (enc28j60_registers_t a, char bits)
Clears the SFR bit field.
static uint16_t ENC28_PhyRead (enc28j60_phy_registers_t a)
Reads the Physical Layer (PHY) register.
static void ENC28_PhyWrite (enc28j60_phy_registers_t a, uint16_t d)
Writes the PHY register.
static void ENC28_BankSel (enc28j60_registers_t r)
Selects the bank.
static void ETH_CloseSPI (void)
Releases the Serial Peripheral Interface (SPI) bus.
static void ETH_OpenSPI (void)
Connects the SPI bus.
1.4.1.1.5 Variables
uint8_t Control_Byte
ENC28J60 Control Byte.
1.4.1.2 Definition Documentation
1.4.1.2.1 ETH_ALLOCATED
#define ETH_ALLOCATED (0x0001 << 2)
Flag for pool management. Set to either free or allocated.
1.4.1.2.2 ETH_NCS_HIGH
#define ETH_NCS_HIGH( ) do{ETH_CS_SetHigh();} while(0)
Sets Ethernet Chip Select to high.
1.4.1.2.3 ETH_NCS_LOW
#define ETH_NCS_LOW( ) do{ETH_CS_SetLow();} while(0)
Sets Ethernet Chip Select to low.
1.4.1.2.4 ETH_SPI_READ8
#define ETH_SPI_READ8( ) SPI1_Host.ByteExchange(0)
Reads the SPI byte.
1.4.1.2.5 ETH_SPI_WRITE8
#define ETH_SPI_WRITE8( a) SPI1_Host.ByteExchange(a)
Writes the SPI byte.
1.4.1.2.6 ETH_TX_QUEUED
#define ETH_TX_QUEUED (0x0001 << 1)
Packet complete, in queue for transmit.
1.4.1.2.7 ETH_WRITE_IN_PROGRESS
#define ETH_WRITE_IN_PROGRESS (0x0001 << 0)
Packet write in progress, not ready for transmit.
1.4.1.3 Function Documentation
1.4.1.3.1 ENC28_BankSel()
static void ENC28_BankSel (enc28j60_registers_t r)[static]
Selects the bank.
| r |
register |
None. |
1.4.1.3.2 ENC28_Bfc()
static void ENC28_Bfc (enc28j60_registers_t a, char bits)[static]
Clears the SFR bit field.
| a |
register |
| bits |
None. |
1.4.1.3.3 ENC28_Bfs()
static void ENC28_Bfs (enc28j60_registers_t a, char bits)[static]
Sets the SFR bit field.
| a |
register |
| bits |
None. |
1.4.1.3.4 ENC28_PhyRead()
static uint16_t ENC28_PhyRead (enc28j60_phy_registers_t a)[static]
Reads the Physical Layer (PHY) register.
| a |
register |
Register data. |
1.4.1.3.5 ENC28_PhyWrite()
static void ENC28_PhyWrite (enc28j60_phy_registers_t a, uint16_t d)[static]
Writes the PHY register.
| a |
register |
| d |
data |
None. |
1.4.1.3.6 ENC28_Rcr16()
static uint16_t ENC28_Rcr16 (enc28j60_registers_t a)[static]
Reads two bytes from SFRs.
| a |
register |
Two bytes of SFR value. |
1.4.1.3.7 ENC28_Rcr8()
static uint8_t ENC28_Rcr8 (enc28j60_registers_t a)[static]
Reads one byte from Special Function Register (SFR).
| a |
register |
One byte of SFR value. |
1.4.1.3.8 ENC28_Wcr16()
static void ENC28_Wcr16 (enc28j60_registers_t a, uint16_t v)[static]
Writes two bytes to SFRs.
| a |
register |
| v |
16-bit value |
None. |
1.4.1.3.9 ENC28_Wcr8()
static void ENC28_Wcr8 (enc28j60_registers_t a, uint8_t v)[static]
Writes one byte to SFRs.
| a |
register |
| v |
8-bit value |
None. |
1.4.1.3.10 ETH_CloseSPI()
static void ETH_CloseSPI (void )[static]
Releases the Serial Peripheral Interface (SPI) bus.
| None. |
None. |
1.4.1.3.11 ETH_ComputeChecksum()
static uint16_t ETH_ComputeChecksum (uint16_t len, uint16_t seed)[static]
Calculates the checksum.
| len |
length |
| seed |
Checksum. |
1.4.1.3.12 ETH_NewPacket()
txPacket_t * ETH_NewPacket (void )
Allocates a new packet element and links it to the chained list.
| None. |
Packet address. |
1.4.1.3.13 ETH_OpenSPI()
static void ETH_OpenSPI (void )[static]
Connects the SPI bus.
| None. |
None. |
1.4.1.3.14 ETH_PacketListReset()
void ETH_PacketListReset (void )
Resets the Ethernet packet list.
| None. |
None. |
1.4.1.3.15 ETH_RemovePacket()
void ETH_RemovePacket (txPacket_t * pPacket)
Deallocates a packet element and unlinks it from the chained list.
| pPacket |
packetHandle |
None. |
1.4.1.3.16 ETH_SendQueued()
phy_error_msg ETH_SendQueued (void )
Enqueues the latest written packet and starts the transmission of a queued packet.
| None. |
| PHY_SUCCESS | |
| PHY_BUFFER_BUSY |
1.4.1.3.17 ETH_Shift_Tx_Packets()
phy_error_msg ETH_Shift_Tx_Packets (void )
Copies the queued packets to the TX Buffer start address using the DMA setup.
| None. |
| PHY_SUCCESS | |
| PHY_DMA_TIMEOUT |
1.4.1.4 Enumeration Type Documentation
1.4.1.4.1 enc28j60_phy_registers_t
enum enc28j60_phy_registers_t
ENC28J60 PHY register addresses.
| J60_PHCON1 |
PHY Control Register 1 |
| J60_PHSTAT1 |
Physical Layer Status Register 1 |
| J60_PHID1 |
PHY Identifier |
| J60_PHID2 |
PHY Identifier, P/N, and Revision |
| J60_PHCON2 |
PHY Control Register 2 |
| J60_PHSTAT2 |
Physical Layer Status Register 2 |
| J60_PHIE |
PHY Interrupt Enable Register |
| J60_PHIR |
PHY Interrupt Request Register |
| J60_PHLCON |
PHY Module LED Control Register |
1.4.1.4.2 enc28j60_registers_t
enum enc28j60_registers_t
ENC28J60 registers.
| J60_ERDPTL |
Bank 0: Read Pointer Low Byte |
| J60_ERDPTH |
Bank 0: Read Pointer High Byte |
| J60_EWRPTL |
Bank 0: Write Pointer Low Byte |
| J60_EWRPTH |
Bank 0: Write Pointer High Byte |
| J60_ETXSTL |
Bank 0: TX Start Low Byte |
| J60_ETXSTH |
Bank 0: TX Start High Byte |
| J60_ETXNDL |
Bank 0: TX End Low Byte |
| J60_ETXNDH |
Bank 0: TX End High Byte |
| J60_ERXSTL |
Bank 0: RX Start Low Byte |
| J60_ERXSTH |
Bank 0: RX Start High Byte |
| J60_ERXNDL |
Bank 0: RX End Low Byte |
| J60_ERXNDH |
Bank 0: RX End High Byte |
| J60_ERXRDPTL |
Bank 0: RX RD Pointer Low Byte |
| J60_ERXRDPTH |
Bank 0: RX RD Pointer High Byte |
| J60_ERXWRPTL |
Bank 0: RX WR Pointer Low Byte |
| J60_ERXWRPTH |
Bank 0: RX WR Pointer High Byte |
| J60_EDMASTL |
Bank 0: DMA Start Low Byte |
| J60_EDMASTH |
Bank 0: DMA Start High Byte |
| J60_EDMANDL |
Bank 0: DMA End Low Byte |
| J60_EDMANDH |
Bank 0: DMA End High Byte |
| J60_EDMADSTL |
Bank 0: DMA Destination Low Byte |
| J60_EDMADSTH |
Bank 0: DMA Destination High Byte |
| J60_EDMACSL |
Bank 0: DMA Checksum Low Byte |
| J60_EDMACSH |
Bank 0: DMA Checksum High Byte |
| RSRV_018 |
Bank 0: Reserved |
| RSRV_019 |
Bank 0: Reserved |
| RSRV_01A |
Bank 0: Reserved |
| J60_EHT0 |
Bank 1: Hash Table Byte 0 |
| J60_EHT1 |
Bank 1: Hash Table Byte 1 |
| J60_EHT2 |
Bank 1: Hash Table Byte 2 |
| J60_EHT3 |
Bank 1: Hash Table Byte 3 |
| J60_EHT4 |
Bank 1: Hash Table Byte 4 |
| J60_EHT5 |
Bank 1: Hash Table Byte 5 |
| J60_EHT6 |
Bank 1: Hash Table Byte 6 |
| J60_EHT7 |
Bank 1: Hash Table Byte 7 |
| J60_EPMM0 |
Bank 1: Pattern Match Mask Byte 0 |
| J60_EPMM1 |
Bank 1: Pattern Match Mask Byte 1 |
| J60_EPMM2 |
Bank 1: Pattern Match Mask Byte 2 |
| J60_EPMM3 |
Bank 1: Pattern Match Mask Byte 3 |
| J60_EPMM4 |
Bank 1: Pattern Match Mask Byte 4 |
| J60_EPMM5 |
Bank 1: Pattern Match Mask Byte 5 |
| J60_EPMM6 |
Bank 1: Pattern Match Mask Byte 6 |
| J60_EPMM7 |
Bank 1: Pattern Match Mask Byte 7 |
| J60_EPMCSL |
Bank 1: Pattern Match Checksum Low Byte |
| J60_EPMCSH |
Bank 1: Pattern Match Checksum High Byte |
| RSRV_112 |
Bank 1: Reserved |
| RSRV_113 |
Bank 1: Reserved |
| J60_EPMOL |
Bank 1: Pattern Match Offset Low Byte |
| J60_EPMOH |
Bank 1: Pattern Match Offset High Byte |
| RSRV_116 |
Bank 1: Reserved |
| RSRV_117 |
Bank 1: Reserved |
| J60_ERXFCON |
Bank 1: Ethernet Receive Filter Control Register |
| J60_EPKTCNT |
Bank 1: Ethernet Packet Count |
| RSRV_11A |
Bank 1: Reserved |
| J60_MACON1 |
Bank 2: MAC Control Register 1 |
| RSRV_201 |
Bank 2: Reserved |
| J60_MACON3 |
Bank 2: MAC Control Register 3 |
| J60_MACON4 |
Bank 2: MAC Control Register 4 |
| J60_MABBIPG |
Bank 2: Back-to-Back Inter-Packet Gap |
| RSRV_205 |
Bank 2: Reserved |
| J60_MAIPGL |
Bank 2: Non-Back-to-Back Inter-Packet Gap Low Byte |
| J60_MAIPGH |
Bank 2: Non-Back-to-Back Inter-Packet Gap High Byte |
| J60_MACLCON1 |
Bank 2: Retransmission Maximum |
| J60_MACLCON2 |
Bank 2: Collision Window |
| J60_MAMXFLL |
Bank 2: Maximum Frame Length Low Byte |
| J60_MAMXFLH |
Bank 2: Maximum Frame Length High Byte |
| RSRV_20C |
Bank 2: Reserved |
| RSRV_20D |
Bank 2: Reserved |
| RSRV_20E |
Bank 2: Reserved |
| RSRV_20F |
Bank 2: Reserved |
| RSRV_210 |
Bank 2: Reserved |
| RSRV_211 |
Bank 2: Reserved |
| J60_MICMD |
Bank 2: MII Command Register |
| RSRV_213 |
Bank 2: Reserved |
| J60_MIREGADR |
Bank 2: MII Register Address |
| RSRV_215 |
Bank 2: Reserved |
| J60_MIWRL |
Bank 2: MII Write Data Low Byte |
| J60_MIWRH |
Bank 2: MII Write Data High Byte |
| J60_MIRDL |
Bank 2: MII Read Data Low Byte |
| J60_MIRDH |
Bank 2: MII Read Data High Byte |
| RSRV_21A |
Bank 2: Reserved |
| J60_MAADR5 |
Bank 3: MAC Address Byte 5 |
| J60_MAADR6 |
Bank 3: MAC Address Byte 6 |
| J60_MAADR3 |
Bank 3: MAC Address Byte 3 |
| J60_MAADR4 |
Bank 3: MAC Address Byte 4 |
| J60_MAADR1 |
Bank 3: MAC Address Byte 1 |
| J60_MAADR2 |
Bank 3: MAC Address Byte 2 |
| J60_EBSTSD |
Bank 3: Built-in Self-Test Fill Seed |
| J60_EBSTCON |
Bank 3: Ethernet Self-Test Control Register |
| J60_EBSTCSL |
Bank 3: Built-in Self-Test Checksum Low Byte |
| J60_EBSTCSH |
Bank 3: Built-in Self-Test Checksum High Byte |
| J60_MISTAT |
Bank 3: MII Status Register |
| RSRV_30B |
Bank 3: Reserved |
| RSRV_30C |
Bank 3: Reserved |
| RSRV_30D |
Bank 3: Reserved |
| RSRV_30E |
Bank 3: Reserved |
| RSRV_30F |
Bank 3: Reserved |
| RSRV_310 |
Bank 3: Reserved |
| RSRV_311 |
Bank 3: Reserved |
| J60_EREVID |
Bank 3: Ethernet Revision ID |
| RSRV_313 |
Bank 3: Reserved |
| RSRV_314 |
Bank 3: Reserved |
| J60_ECOCON |
Bank 3: Clock Output Control Register |
| RSRV_316 |
Bank 3: Reserved |
| J60_EFLOCON |
Bank 3: Ethernet Flow Control Register |
| J60_EPAUSL |
Bank 3: Pause Timer Value Low Byte |
| J60_EPAUSH |
Bank 3: Pause Timer Value High Byte |
| RSRV_31A |
Bank 3: Reserved |
| J60_EIE |
Common Bank Registers: Ethernet Interrupt Enable Register |
| J60_EIR |
Common Bank Registers: Ethernet Interrupt Request (Flag) Register |
| J60_ESTAT |
Common Bank Registers: Ethernet Status Register |
| J60_ECON2 |
Common Bank Registers: Ethernet Control Register 2 |
| J60_ECON1 |
Common Bank Registers: Ethernet Control Register 1 |
1.4.1.4.3 sfr_bank_t
enum sfr_bank_t
SFR banks.
Special Function Register (SFR) Banks.
| sfr_bank0 |
Bank 0 |
| sfr_bank1 |
Bank 1 |
| sfr_bank2 |
Bank 2 |
| sfr_bank3 |
Bank 3 |
| sfr_common |
Common Set of Registers (last five locations of each bank) |
| sfr_bank0 |
Bank 0 |
| sfr_bank1 |
Bank 1 |
| sfr_bank2 |
Bank 2 |
| sfr_bank3 |
Bank 3 |
| sfr_common |
Common Set of Registers (last five locations of each bank) |
1.4.1.4.4 spi_inst_t
enum spi_inst_t
SPI instructions.
| rcr_inst |
Read Control Register |
| rbm_inst |
Read Buffer Memory |
| wcr_inst |
Write Control Register |
| wbm_inst |
Write Buffer Memory |
| bfs_inst |
Bit Field Set |
| bfc_inst |
Bit Field Clear |
| src_inst |
System Reset Command (Soft Reset) |
1.4.1.5 Variable Documentation
1.4.1.5.1 Control_Byte
Control_Byte
ENC28J60 Control Byte.
1.4.2 ENCX24J600
This file provides register definitions for the ENCx24J600 controller.
1.4.2.1 Module description
This file provides register definitions for the ENCx24J600 controller.
1.4.2.1.1 Data structures
union receiveStatusVector_t
ENC28J60 receive status vector.
1.4.2.1.2 Definitions
#define ETH_WRITE_IN_PROGRESS (0x0001 << 0)
Packet write in progress, not ready for transmit.
#define ETH_TX_QUEUED (0x0001 << 1)
Packet in queue for transmit.
#define ETH_ALLOCATED (0x0001 << 2)
Flag for pool management. Set to either free or allocated.
#define ETH_NCS_HIGH() do{ETH_CS_SetHigh();} while(0)
Sets Ethernet Chip Select to high.
#define ETH_NCS_LOW() do{ETH_CS_SetLow();} while(0)
Sets Ethernet Chip Select to low.
#define ETH_READ8() SPI1_Host.ByteExchange(0)
Reads the Serial Peripheral Interface (SPI) byte.
#define ETH_WRITE8(a) SPI1_Host.ByteExchange(a)
Packet write in progress, not ready for transmit.
#define TXSTART 0x0000ul
Transmit buffer start.
#define TXEND 0x15FFul
Transmit buffer end.
#define RXSTART 0x1600ul
Receive buffer start (must be an even memory address).
#define RXEND (RAMSIZE_ETH - 2)
Receive buffer end.
#define PHCON1_PSLEEP 0x0800
Bit mask for PHY Sleep Enable bit. Physical Layer (PHY) power is down.
#define PHCON1_PWAKE 0xF7FF
Bit mask for PHY Wake-Up as a normal operation.
1.4.2.1.3 Enumerations
enum encX24J600_registers_t { XJ600_ETXSTL = (SFR_BANK0 | 0x00), XJ600_ETXLENL = (SFR_BANK0 | 0x02), XJ600_ERXSTL = (SFR_BANK0 | 0x04), XJ600_ERXTAILL = (SFR_BANK0 | 0x06), XJ600_ERXHEADL = (SFR_BANK0 | 0x08), XJ600_EDMASTL = (SFR_BANK0 | 0x0A), XJ600_EDMALENL = (SFR_BANK0 | 0x0C), XJ600_EDMADSTL = (SFR_BANK0 | 0x0E), XJ600_EDMACSL = (SFR_BANK0 | 0x10), XJ600_ETXSTATL = (SFR_BANK0 | 0x12), XJ600_ETXWIREL = (SFR_BANK0 | 0x14), XJ600_EHT1L = (SFR_BANK1 | 0x00), XJ600_EHT2L = (SFR_BANK1 | 0x02), XJ600_EHT3L = (SFR_BANK1 | 0x04), XJ600_EHT4L = (SFR_BANK1 | 0x06), XJ600_EPMM1L = (SFR_BANK1 | 0x08), XJ600_EPMM2L = (SFR_BANK1 | 0x0A), XJ600_EPMM3L = (SFR_BANK1 | 0x0C), XJ600_EPMM4L = (SFR_BANK1 | 0x0E), XJ600_EPMCSL = (SFR_BANK1 | 0x10), XJ600_EPMOL = (SFR_BANK1 | 0x12), XJ600_ERXFCONL = (SFR_BANK1 | 0x14), XJ600_MACON1L = (SFR_BANK2 | 0x00), XJ600_MACON2L = (SFR_BANK2 | 0x02), XJ600_MABBIPGL = (SFR_BANK2 | 0x04), XJ600_MAIPGL = (SFR_BANK2 | 0x06), XJ600_MACLCONL = (SFR_BANK2 | 0x08), XJ600_MAMXFLL = (SFR_BANK2 | 0x0A), XJ600_MICMDL = (SFR_BANK2 | 0x12), XJ600_MIREGADRL = (SFR_BANK2 | 0x14), XJ600_MAADR3L = (SFR_BANK3 | 0x00), XJ600_MAADR3H = (SFR_BANK3 | 0x01), XJ600_MAADR2L = (SFR_BANK3 | 0x02), XJ600_MAADR2H = (SFR_BANK3 | 0x03), XJ600_MAADR1L = (SFR_BANK3 | 0x04), XJ600_MAADR1H = (SFR_BANK3 | 0x05), XJ600_MIWRL = (SFR_BANK3 | 0x06), XJ600_MIRDL = (SFR_BANK3 | 0x08), XJ600_MISTATL = (SFR_BANK3 | 0x0A), XJ600_EPAUSL = (SFR_BANK3 | 0x0C), XJ600_ECON2L = (SFR_BANK3 | 0x0E), XJ600_ERXWML = (SFR_BANK3 | 0x10), XJ600_EIEL = (SFR_BANK3 | 0x12), XJ600_EIDLEDL = (SFR_BANK3 | 0x14), XJ600_EGPDATAL = (UNBANKED | 0x00), XJ600_ERXDATAL = (UNBANKED | 0x02), XJ600_EUDADATAL = (UNBANKED | 0x04), XJ600_EGPRDPTL = (UNBANKED | 0x06), XJ600_EGPWRPTL = (UNBANKED | 0x08), XJ600_ERXRDPTL = (UNBANKED | 0x0A), XJ600_ERXWRPTL = (UNBANKED | 0x0C), XJ600_EUDARDPTL = (UNBANKED | 0x0E), XJ600_EUDAWRPTL = (UNBANKED | 0x10), XJ600_EUDASTL = (SFR_COMMON | 0x16), XJ600_EUDANDL = (SFR_COMMON | 0x18), XJ600_ESTATL = (SFR_COMMON | 0x1A), XJ600_EIRL = (SFR_COMMON | 0x1C), XJ600_ECON1L = (SFR_COMMON | 0x1E) }
SFR addresses for the ENCx24J600 SPI mode.
enum encX24J600_1_byte_instructions_t { b0sel_inst = 0b11000000, b1sel_inst = 0b11000010, b2sel_inst = 0b11000100, b3sel_inst = 0b11000110, setethrst_inst = 0b11001010, fcdisable_inst = 0b11100000, fcsingle_inst = 0b11100010, fcmultiple_inst = 0b11100100, fcclear_inst = 0b11100110, setpktdec_inst = 0b11001100, dmastop_inst = 0b11010010, dmacksum_inst = 0b11011000, dmacksums_inst = 0b11011010, dmacopy_inst = 0b11011100, dmacopys_inst = 0b11011110, settxrts_inst = 0b11010100, enablerx_inst = 0b11101000, disablerx_inst = 0b11101010, seteie_inst = 0b11101100, clreie_inst = 0b11101110 }
SPI single byte instructions.
enum encX24J600_2_byte_instructions_t { rbsel_inst = 0b11001000 }
SPI two byte instructions.
enum encX24J600_3_byte_instructions_t { rgprdpt_inst = 0b01100010, rrxrdpt_inst = 0b01100110, rgpwrpt_inst = 0b01101110, rrxwrpt_inst = 0b01110010, rudawrpt_inst = 0b01110110, wgprdpt_inst = 0b01100000, wrxrdpt_inst = 0b01100100, wgpwrpt_inst = 0b01101100, wrxwrpt_inst = 0b01110000, wudawrpt_inst = 0b01110100 }
SPI three byte instructions.
enum encX24J600_N_byte_instructions_t { rcr_inst = 0b00000000, wcr_inst = 0b01000000, bfs_inst = 0b10000000, bfc_inst = 0b10100000, rcru_inst = 0b00100000, wcru_inst = 0b00100010, bfsu_inst = 0b00100100, bfcu_inst = 0b00100110, rgpdata_inst = 0b00101000, rrxdata_inst = 0b00101100, rudadata_inst = 0b00110000, wgpdata_inst = 0b00101010, wrxdata_inst = 0b00101110, wudadata_inst = 0b00110010 }
SPI N byte instructions.
enum encX24J600_phy_registers_t { PHCON1 = 0x00, PHSTAT1 = 0x01, PHANA = 0x04, PHANLPA = 0x05, PHANE = 0x06, PHCON2 = 0x11, PHSTAT2 = 0x1B, PHSTAT3 = 0x1F }
ENCX24J600 PHY registers.
1.4.2.1.4 Functions
phy_error_msg ETH_SendQueued (void)
Enqueues the latest written packet and starts the transmission of a queued packet.
phy_error_msg ETH_Shift_Tx_Packets (void)
Copies all the queued packets to the TX Buffer start address using the DMA setup.
void ETH_PacketListReset (void)
Resets the Ethernet packet list.
txPacket_t * ETH_NewPacket (void)
Allocates a new packet element and links it to the chained list.
void ETH_RemovePacket (txPacket_t *pPacket)
Deallocates a packet element and unlinks it from the chained list.
static uint16_t ETH_DMAComputeChecksum (uint16_t rxPtr, uint16_t len, uint16_t seed)
Calculates the checksum.
static void ETH_CloseSPI (void)
Releases the Serial Peripheral Interface (SPI) bus.
static void ETH_OpenSPI (void)
Connects the SPI bus.
static void waitForDMA (void)
Waits for the DMA.
static uint32_t ETH_readLinkStatus (void)
Checks for the link status.
static void ENCx24_BankselSPI (encX24J600_registers_t a)
Selects the SPI bank.
uint16_t ENCx24_Read (encX24J600_registers_t a)
Reads from Special Function Register (SFR).
uint8_t ETH_EdataRead (encX24J600_registers_t a)
Reads the 8-bit data from the ENCx24J600 register (work around for Errata).
void ENCx24_Write (encX24J600_registers_t a, uint16_t data)
Writes to SFRs.
void ENCx24_BFS (encX24J600_registers_t a, uint16_t bitMask)
Sets the SFR bit field.
void ENCx24_BFC (encX24J600_registers_t a, uint16_t bitMask)
Clears the SFR bit field.
uint16_t ENCx24_PhyRead (encX24J600_phy_registers_t a)
Reads the PHY register.
void ENCx24_PHYWrite (encX24J600_phy_registers_t a, uint16_t data)
Writes the PHY register.
uint8_t ETH_MACRead8 (encX24J600_registers_t a)
Reads the 8-bit MAC-related data from ENCx24J600 registers.
void ETH_MACWrite8 (encX24J600_registers_t a, uint8_t data)
Writes the 8-bit MAC-related data to ENCx24J600 registers.
void ETH_SetPktDec (void)
Decrements packet count.
void ETH_SetRXptr (uint16_t address)
RX packet read pointer.
void ETH_Set_TXRTS (void)
Packet transmission request.
1.4.2.2 Definition Documentation
1.4.2.2.1 ETH_ALLOCATED
#define ETH_ALLOCATED (0x0001 << 2)
Flag for pool management. Set to either free or allocated.
1.4.2.2.2 ETH_NCS_HIGH
#define ETH_NCS_HIGH( ) do{ETH_CS_SetHigh();} while(0)
Sets Ethernet Chip Select to high.
1.4.2.2.3 ETH_NCS_LOW
#define ETH_NCS_LOW( ) do{ETH_CS_SetLow();} while(0)
Sets Ethernet Chip Select to low.
1.4.2.2.4 ETH_READ8
#define ETH_READ8( ) SPI1_Host.ByteExchange(0)
Reads the Serial Peripheral Interface (SPI) byte.
1.4.2.2.5 ETH_TX_QUEUED
#define ETH_TX_QUEUED (0x0001 << 1)
Packet in queue for transmit.
1.4.2.2.6 ETH_WRITE8
#define ETH_WRITE8( a) SPI1_Host.ByteExchange(a)
Packet write in progress, not ready for transmit.
1.4.2.2.7 ETH_WRITE_IN_PROGRESS
#define ETH_WRITE_IN_PROGRESS (0x0001 << 0)
Packet write in progress, not ready for transmit.
1.4.2.2.8 PHCON1_PSLEEP
#define PHCON1_PSLEEP 0x0800
Bit mask for PHY Sleep Enable bit. Physical Layer (PHY) power is down.
1.4.2.2.9 PHCON1_PWAKE
#define PHCON1_PWAKE 0xF7FF
Bit mask for PHY Wake-Up as a normal operation.
1.4.2.2.10 RXEND
#define RXEND (RAMSIZE_ETH - 2)
Receive buffer end.
1.4.2.2.11 RXSTART
#define RXSTART 0x1600ul
Receive buffer start (must be an even memory address).
1.4.2.2.12 TXEND
#define TXEND 0x15FFul
Transmit buffer end.
1.4.2.2.13 TXSTART
#define TXSTART 0x0000ul
Transmit buffer start.
1.4.2.3 Function Documentation
1.4.2.3.1 ENCx24_BankselSPI()
static void ENCx24_BankselSPI (encX24J600_registers_t a)[static]
Selects the SPI bank.
| a |
register |
None. |
1.4.2.3.2 ENCx24_BFC()
void ENCx24_BFC (encX24J600_registers_t a, uint16_t bitMask)
Clears the SFR bit field.
| a |
register |
| bitMask |
None. |
1.4.2.3.3 ENCx24_BFS()
void ENCx24_BFS (encX24J600_registers_t a, uint16_t bitMask)
Sets the SFR bit field.
| a |
register |
| bitMask |
None. |
1.4.2.3.4 ENCx24_PhyRead()
uint16_t ENCx24_PhyRead (encX24J600_phy_registers_t a)
Reads the PHY register.
| a |
register |
Two bytes of data. |
1.4.2.3.5 ENCx24_PHYWrite()
void ENCx24_PHYWrite (encX24J600_phy_registers_t a, uint16_t data)
Writes the PHY register.
| a |
register |
| data |
None. |
1.4.2.3.6 ENCx24_Read()
uint16_t ENCx24_Read (encX24J600_registers_t a)
Reads from Special Function Register (SFR).
| a |
register |
Two bytes of SFR value. |
1.4.2.3.7 ENCx24_Write()
void ENCx24_Write (encX24J600_registers_t a, uint16_t data)
Writes to SFRs.
| a |
register |
| data |
None. |
1.4.2.3.8 ETH_CloseSPI()
static void ETH_CloseSPI (void )[static]
Releases the Serial Peripheral Interface (SPI) bus.
| None. |
None. |
1.4.2.3.9 ETH_DMAComputeChecksum()
static uint16_t ETH_DMAComputeChecksum (uint16_t rxPtr, uint16_t len, uint16_t seed)[static]
Calculates the checksum.
| rxPtr |
RX pointer |
| len |
length |
| seed |
Checksum. |
1.4.2.3.10 ETH_EdataRead()
uint8_t ETH_EdataRead (encX24J600_registers_t a)
Reads the 8-bit data from the ENCx24J600 register (work around for Errata).
| a |
register |
One byte of data. |
1.4.2.3.11 ETH_MACRead8()
uint8_t ETH_MACRead8 (encX24J600_registers_t a)
Reads the 8-bit MAC-related data from ENCx24J600 registers.
| a |
register |
One byte of data. |
1.4.2.3.12 ETH_MACWrite8()
void ETH_MACWrite8 (encX24J600_registers_t a, uint8_t data)
Writes the 8-bit MAC-related data to ENCx24J600 registers.
| a |
register |
| data |
None. |
1.4.2.3.13 ETH_NewPacket()
txPacket_t* ETH_NewPacket (void )
Allocates a new packet element and links it to the chained list.
| None. |
Packet address. |
1.4.2.3.14 ETH_OpenSPI()
static void ETH_OpenSPI (void )[static]
Connects the SPI bus.
| None. |
None. |
1.4.2.3.15 ETH_PacketListReset()
void ETH_PacketListReset (void )
Resets the Ethernet packet list.
| None. |
None. |
1.4.2.3.16 ETH_readLinkStatus()
inline static uint32_t ETH_readLinkStatus (void )
Checks for the link status.
| None. |
| PHY_SUCCESS |
link found |
| PHY_LINK_NOT_FOUND |
link is not present |
1.4.2.3.17 ETH_RemovePacket()
void ETH_RemovePacket (txPacket_t * pPacket)
Deallocates a packet element and unlinks it from the chained list.
| *pPacket |
packetHandle |
None. |
1.4.2.3.18 ETH_SendQueued()
phy_error_msg ETH_SendQueued (void )
Enqueues the latest written packet and starts the transmission of a queued packet.
| None. |
| PHY_SUCCESS | |
| PHY_BUFFER_BUSY |
1.4.2.3.19 ETH_Set_TXRTS()
void ETH_Set_TXRTS (void )
Packet transmission request.
| None. |
None. |
1.4.2.3.20 ETH_SetPktDec()
void ETH_SetPktDec (void )
Decrements packet count.
| None. |
None. |
1.4.2.3.21 ETH_SetRXptr()
void ETH_SetRXptr (uint16_t address)
RX packet read pointer.
| address |
None. |
1.4.2.3.22 ETH_Shift_Tx_Packets()
phy_error_msg ETH_Shift_Tx_Packets (void )
Copies all the queued packets to the TX Buffer start address using the DMA setup.
| None. |
| PHY_SUCCESS | |
| PHY_DMA_TIMEOUT |
1.4.2.3.23 waitForDMA()
inline static void waitForDMA (void )
Waits for the DMA.
| None. |
None. |
1.4.2.4 Enumeration Type Documentation
1.4.2.4.1 encX24J600_1_byte_instructions_t
enum encX24J600_1_byte_instructions_t
SPI single byte instructions.
| b0sel_inst |
Bank 0 Select |
| b1sel_inst |
Bank 1 Select |
| b2sel_inst |
Bank 2 Select |
| b3sel_inst |
Bank 3 Select |
| setethrst_inst |
System Reset |
| fcdisable_inst |
Flow Control Disable |
| fcsingle_inst |
Flow Control Single |
| fcmultiple_inst |
Flow Control Multiple |
| fcclear_inst |
Flow Control Clear |
| setpktdec_inst |
Decrement Packet Counter |
| dmastop_inst |
DMA Stop |
| dmacksum_inst |
DMA Start Checksum |
| dmacksums_inst |
DMA Start Checksum with Seed |
| dmacopy_inst |
DMA Start Copy |
| dmacopys_inst |
DMA Start Copy and Checksum with Seed |
| settxrts_inst |
Request Packet Transmission |
| enablerx_inst |
Enable RX |
| disablerx_inst |
Disable RX |
| seteie_inst |
Enable Interrupts |
| clreie_inst |
Disable Interrupts |
1.4.2.4.2 encX24J600_2_byte_instructions_t
enum encX24J600_2_byte_instructions_t
SPI two byte instructions.
| rbsel_inst |
Read Bank Select |
1.4.2.4.3 encX24J600_3_byte_instructions_t
enum encX24J600_3_byte_instructions_t
SPI three byte instructions.
| rgprdpt_inst |
Read EGPRDPT |
| rrxrdpt_inst |
Read ERXRDPT |
| rgpwrpt_inst |
Read EGPWRPT |
| rrxwrpt_inst |
Read ERXRDPT |
| rudawrpt_inst |
Read EUDAWRPT |
| wgprdpt_inst |
Write EGPRDPT |
| wrxrdpt_inst |
Write ERXRDPT |
| wgpwrpt_inst |
Write EGPWRPT |
| wrxwrpt_inst |
Write ERXWRPT |
| wudawrpt_inst |
Write EUDAWRPT |
1.4.2.4.4 encX24J600_N_byte_instructions_t
enum encX24J600_N_byte_instructions_t
SPI N byte instructions.
| rcr_inst |
Banked register read |
| wcr_inst |
Banked register write |
| bfs_inst |
Banked bit set |
| bfc_inst |
Banked bit clear |
| rcru_inst |
Unbanked SFR operation |
| wcru_inst |
Unbanked SFR writes |
| bfsu_inst |
Unbanked bit set |
| bfcu_inst |
Unbanked bit clear |
| rgpdata_inst |
SRAM data EGPDATA read |
| rrxdata_inst |
SRAM data RXDATA read |
| rudadata_inst |
SRAM data UDADATA read |
| wgpdata_inst |
SRAM writes |
| wrxdata_inst |
SRAM data write from ERXDATA |
| wudadata_inst |
SRAM data write from EUDADATA |
1.4.2.4.5 encX24J600_phy_registers_t
enum encX24J600_phy_registers_t
ENCX24J600 PHY registers.
| PHCON1 |
PHY Control Register 1 |
| PHSTAT1 |
Physical Layer Status Register 1 |
| PHANA |
PHY Auto-Negotiation Advertisement Register |
| PHANLPA |
PHY Auto-Negotiation Link Partner Ability Register |
| PHANE |
PHY Auto-Negotiation Expansion Register |
| PHCON2 |
PHY Control Register 2 |
| PHSTAT2 |
Physical Layer Status Register 2 |
| PHSTAT3 |
Physical Layer Status Register 3 |
1.4.2.4.6 encX24J600_registers_t
enum encX24J600_registers_t
SFR addresses for the ENCx24J600 SPI mode.
| XJ600_ETXSTL |
TX Start Address |
| XJ600_ETXLENL |
TX Length |
| XJ600_ERXSTL |
RX Buffer Start Address |
| XJ600_ERXTAILL |
RX Tail Pointer |
| XJ600_ERXHEADL |
RX Head Pointer |
| XJ600_EDMASTL |
DMA Start Address |
| XJ600_EDMALENL |
DMA Length |
| XJ600_EDMADSTL |
DMA Destination Address |
| XJ600_EDMACSL |
DMA Checksum |
| XJ600_ETXSTATL |
TX Status |
| XJ600_ETXWIREL |
Transmit Byte Count on Wire (including collision bytes) |
| XJ600_EHT1L |
Hash Table Filter 1 |
| XJ600_EHT2L |
Hash Table Filter 2 |
| XJ600_EHT3L |
Hash Table Filter 3 |
| XJ600_EHT4L |
Hash Table Filter 4 |
| XJ600_EPMM1L |
Pattern Match Filter Mask 1 |
| XJ600_EPMM2L |
Pattern Match Filter Mask 2 |
| XJ600_EPMM3L |
Pattern Match Filter Mask 3 |
| XJ600_EPMM4L |
Pattern Match Filter Mask 4 |
| XJ600_EPMCSL |
Pattern Match Filter Checksum |
| XJ600_EPMOL |
Pattern Match Filter Offset |
| XJ600_ERXFCONL |
Ethernet RX Filter Control Register |
| XJ600_MACON1L |
MAC Control Register 1 |
| XJ600_MACON2L |
MAC Control Register 2 |
| XJ600_MABBIPGL |
MAC Back-to-Back Inter-Packet Gap |
| XJ600_MAIPGL |
MAC Inter-Packet Gap |
| XJ600_MACLCONL |
MAC Colision Control Register |
| XJ600_MAMXFLL |
MAC Maximum Frame Length |
| XJ600_MICMDL |
MII Management Command |
| XJ600_MIREGADRL |
MII Management Adresses |
| XJ600_MAADR3L |
MAC Address Byte 5 |
| XJ600_MAADR3H |
MAC Address Byte 6 |
| XJ600_MAADR2L |
MAC Address Byte 3 |
| XJ600_MAADR2H |
MAC Address Byte 4 |
| XJ600_MAADR1L |
MAC Address Byte 1 |
| XJ600_MAADR1H |
MAC Address Byte 2 |
| XJ600_MIWRL |
MII Management Write Data |
| XJ600_MIRDL |
MII Management Read Data |
| XJ600_MISTATL |
MII Management Status Register |
| XJ600_EPAUSL |
Pause Timer Value |
| XJ600_ECON2L |
Ethernet Control Register 2 |
| XJ600_ERXWML |
Receive Watermark |
| XJ600_EIEL |
Ethernet Interrupt Enable Register |
| XJ600_EIDLEDL |
Ethernet ID Status/LED Control Register |
| XJ600_EGPDATAL |
Use the SRAM Instructions |
| XJ600_ERXDATAL |
Use the SRAM Instructions |
| XJ600_EUDADATAL |
Use the SRAM Instructions |
| XJ600_EGPRDPTL |
General Purpose Data Window Register |
| XJ600_EGPWRPTL |
General Purpose Window Write Pointer |
| XJ600_ERXRDPTL |
RX Window Read Pointer |
| XJ600_ERXWRPTL |
RX Window Write Pointer |
| XJ600_EUDARDPTL |
UDA Window Read Pointer |
| XJ600_EUDAWRPTL |
UDA Window Write Pointer |
| XJ600_EUDASTL |
User-Defined Area Start Pointer |
| XJ600_EUDANDL |
User-Defined Area End Pointer |
| XJ600_ESTATL |
Ethernet Status Register |
| XJ600_EIRL |
Ethernet Interrupt Flag Register 1 |
| XJ600_ECON1L |
Ethernet Control Register 1 |
1.4.3 Ethernet Driver 8-Bit Interface
This file includes definitions of public interface for an Ethernet driver. See individual Ethernet drivers for specific implementations of this interface.
1.4.3.1 Module description
This file includes definitions of public interface for an Ethernet driver. See individual Ethernet drivers for specific implementations of this interface.
1.4.3.1.1 Data structures
union mac48Address_t
MAC Address (48-bits).
union mac64Address_t
MAC Address (64-bits).
1.4.3.1.2 Enumerations
enum phy_error_msg { PHY_ERROR = 0, PHY_SUCCESS, PHY_LINK_NOT_FOUND, PHY_BUFFER_BUSY, PHY_TX_LOGIC_NOT_IDLE, PHY_TX_QUEUED, PHY_DMA_TIMEOUT }
PHY status/errors.
1.4.3.1.3 Functions
void ETH_Init (void)
Sets up the Ethernet and starts the execution. Initializes the TX/RX buffer, the MAC and the PHY.
void ETH_EventHandler (void)
Manages the MAC events. Can be used for polling or for new events in Interrupt Service Routine (ISR).
void ETH_NextPacketUpdate (void)
Updates the pointers for the next available RX packets. Retrieves information about the last received packet and the address of the next ones.
void ETH_ResetReceiver (void)
Resets the receiver buffer.
void ETH_SendSystemReset (void)
Resets the system software.
const mac48Address_t * MAC_getAddress (void)
Returns the MAC address of type mac48Address_t.
uint16_t ETH_ReadBlock (void *buffer, uint16_t length)
Reads a block of data from the RX buffer MAC.
uint8_t ETH_Read8 (void)
Reads one byte of data from the RX buffer MAC.
uint16_t ETH_Read16 (void)
Reads two bytes of data from the RX buffer and returns them in host order.
uint32_t ETH_Read24 (void)
Reads three bytes of data from the RX buffer and returns them in host order.
uint32_t ETH_Read32 (void)
Reads four bytes of data from the RX buffer and returns them in host order.
void ETH_Dump (uint16_t length)
Drops the N bytes from a packet list when the data is lost. Clears a number of bytes (length) from the RX buffer.
void ETH_Flush (void)
Drops the rest of this packet and release the buffer. Clears all bytes from the RX buffer.
uint16_t ETH_GetFreeTxBufferSize (void)
Returns the available space size in the Ethernet TX buffer.
phy_error_msg ETH_WriteStart (const mac48Address_t *dest_mac, uint16_t type)
Starts a packet if the Ethernet transmitter is idle.
uint16_t ETH_WriteString (const char *string)
Writes a string of data into the MAC.
uint16_t ETH_WriteBlock (const char *data, uint16_t length)
Writes a block of data into the TX buffer MAC.
void ETH_Write8 (uint8_t data)
Writes one byte of data into the TX buffer MAC.
void ETH_Write16 (uint16_t data)
Writes two bytes into the TX buffer MAC in Network order.
void ETH_Write24 (uint32_t data)
Writes three bytes into the TX buffer MAC in Network order.
void ETH_Write32 (uint32_t data)
Writes four bytes into the TX buffer MAC in Network order.
void ETH_Insert (char *data, uint16_t len, uint16_t offset)
Inserts N data bytes into a specific offset in the TX buffer/packet.
phy_error_msg ETH_Copy (uint16_t len)
Copies N bytes from the saved read location (RX buffer) into the current TX location (TX buffer) using the DMA set up. This is used for ICMP ECHO to eliminate the need to extract the arbitrary payload.
phy_error_msg ETH_Send (void)
Sends the TX packet. Starts the transmission of packet or queues the packet that has been created.
uint16_t ETH_TxComputeChecksum (uint16_t position, uint16_t length, uint16_t seed)
Calculates the hardware checksum of length bytes starting with the position.
uint16_t ETH_RxComputeChecksum (uint16_t len, uint16_t seed)
Calculates the RX software checksum.
void ETH_GetMAC (uint8_t *macAddr)
Reads the MAC address.
void ETH_SetMAC (uint8_t *macAddr)
Sets the MAC address.
uint16_t ETH_GetWritePtr (void)
Returns the value of the write pointer.
void ETH_SaveRDPT (void)
Saves the receive pointer for copy.
void ETH_ResetReadPtr (void)
Resets the receive pointer to the Init.
uint16_t ETH_GetReadPtr (void)
Returns the value of the read pointer.
void ETH_SetReadPtr (uint16_t rdptr)
Sets the read pointer to a specific address.
uint16_t ETH_GetStatusVectorByteCount (void)
Returns the Status Vector's byte count.
void ETH_SetStatusVectorByteCount (uint16_t bc)
Sets the Status Vector's byte count.
void ETH_ResetByteCount (void)
Resets the driver's byte count.
uint16_t ETH_GetByteCount (void)
Returns the the driver's byte count.
uint16_t ETH_ReadSavedWRPT (void)
Returns the saved write pointer.
void ETH_SaveWRPT (void)
Saves the write pointer for copy.
void ETH_SetRxByteCount (uint16_t count)
Sets the receiver's byte count.
uint16_t ETH_GetRxByteCount (void)
Returns the receiver's byte count.
bool ETH_CheckLinkUp (void)
Checks for the link.
void ETH_TxReset (void)
Resets the transmitter.
void ETH_MoveBackReadPtr (uint16_t offset)
Moves back the read pointer.
1.4.3.2 Function Documentation
1.4.3.2.1 ETH_CheckLinkUp()
bool ETH_CheckLinkUp (void )
Checks for the link.
| None. |
| True |
if the link is present. |
| False |
if the link is not present. |
1.4.3.2.2 ETH_Copy()
phy_error_msg ETH_Copy (uint16_t len)
Copies N bytes from the saved read location (RX buffer) into the current TX location (TX buffer) using the DMA set up. This is used for ICMP ECHO to eliminate the need to extract the arbitrary payload.
| len |
length |
| PHY_SUCCESS | |
| PHY_DMA_TIMEOUT |
1.4.3.2.3 ETH_Dump()
void ETH_Dump (uint16_t length)
Drops the N bytes from a packet list when the data is lost. Clears a number of bytes (length) from the RX buffer.
| length |
None. |
1.4.3.2.4 ETH_EventHandler()
void ETH_EventHandler (void )
Manages the MAC events. Can be used for polling or for new events in Interrupt Service Routine (ISR).
| None. |
None. |
1.4.3.2.5 ETH_Flush()
void ETH_Flush (void )
Drops the rest of this packet and release the buffer. Clears all bytes from the RX buffer.
| None. |
None. |
1.4.3.2.6 ETH_GetByteCount()
uint16_t ETH_GetByteCount (void )
Returns the the driver's byte count.
| None. |
Byte count. |
1.4.3.2.7 ETH_GetFreeTxBufferSize()
uint16_t ETH_GetFreeTxBufferSize (void )
Returns the available space size in the Ethernet TX buffer.
| None. |
Available space left in the TX buffer. |
1.4.3.2.8 ETH_GetMAC()
void ETH_GetMAC (uint8_t * macAddr)
Reads the MAC address.
| *macAddr |
None. |
1.4.3.2.9 ETH_GetReadPtr()
uint16_t ETH_GetReadPtr (void )
Returns the value of the read pointer.
| None. |
Pointer value. |
1.4.3.2.10 ETH_GetRxByteCount()
uint16_t ETH_GetRxByteCount (void )
Returns the receiver's byte count.
| None. |
Byte count. |
1.4.3.2.11 ETH_GetStatusVectorByteCount()
uint16_t ETH_GetStatusVectorByteCount (void )
Returns the Status Vector's byte count.
| None. |
Byte count. |
1.4.3.2.12 ETH_GetWritePtr()
uint16_t ETH_GetWritePtr (void )
Returns the value of the write pointer.
| None. |
Pointer value. |
1.4.3.2.13 ETH_Init()
void ETH_Init (void )
Sets up the Ethernet and starts the execution. Initializes the TX/RX buffer, the MAC and the PHY.
| None. |
None. |
1.4.3.2.14 ETH_Insert()
void ETH_Insert (char * data, uint16_t len, uint16_t offset)
Inserts N data bytes into a specific offset in the TX buffer/packet.
| *data | |
| len |
length |
| offset |
None. |
1.4.3.2.15 ETH_MoveBackReadPtr()
void ETH_MoveBackReadPtr (uint16_t offset)
Moves back the read pointer.
| offset |
None. |
1.4.3.2.16 ETH_NextPacketUpdate()
void ETH_NextPacketUpdate (void )
Updates the pointers for the next available RX packets. Retrieves information about the last received packet and the address of the next ones.
| None. |
None. |
1.4.3.2.17 ETH_Read16()
uint16_t ETH_Read16 (void )
Reads two bytes of data from the RX buffer and returns them in host order.
| None. |
Two bytes of data. |
1.4.3.2.18 ETH_Read24()
uint32_t ETH_Read24 (void )
Reads three bytes of data from the RX buffer and returns them in host order.
| None. |
Three bytes of data. |
1.4.3.2.19 ETH_Read32()
uint32_t ETH_Read32 (void )
Reads four bytes of data from the RX buffer and returns them in host order.
| None. |
Four bytes of data. |
1.4.3.2.20 ETH_Read8()
uint8_t ETH_Read8 (void )
Reads one byte of data from the RX buffer MAC.
| None. |
One byte of data. |
1.4.3.2.21 ETH_ReadBlock()
uint16_t ETH_ReadBlock (void * buffer, uint16_t length)
Reads a block of data from the RX buffer MAC.
| *buffer | |
| length |
Read count. |
1.4.3.2.22 ETH_ReadSavedWRPT()
uint16_t ETH_ReadSavedWRPT (void )
Returns the saved write pointer.
| None. |
Pointer value. |
1.4.3.2.23 ETH_ResetByteCount()
void ETH_ResetByteCount (void )
Resets the driver's byte count.
| None. |
None. |
1.4.3.2.24 ETH_ResetReadPtr()
void ETH_ResetReadPtr (void )
Resets the receive pointer to the Init.
| None. |
None. |
1.4.3.2.25 ETH_ResetReceiver()
void ETH_ResetReceiver (void )
Resets the receiver buffer.
| None. |
None. |
1.4.3.2.26 ETH_RxComputeChecksum()
uint16_t ETH_RxComputeChecksum (uint16_t len, uint16_t seed)
Calculates the RX software checksum.
| len |
length |
| seed |
Checksum. |
1.4.3.2.27 ETH_SaveRDPT()
void ETH_SaveRDPT (void )
Saves the receive pointer for copy.
| None. |
None. |
1.4.3.2.28 ETH_SaveWRPT()
void ETH_SaveWRPT (void )
Saves the write pointer for copy.
| None. |
None. |
1.4.3.2.29 ETH_Send()
phy_error_msg ETH_Send (void )
Sends the TX packet. Starts the transmission of packet or queues the packet that has been created.
| None. |
| PHY_SUCCESS | |
| PHY_BUFFER_BUSY | |
| PHY_LINK_NOT_FOUND | |
| PHY_TX_QUEUED | |
| PHY_TX_LOGIC_NOT_IDLE |
1.4.3.2.30 ETH_SendSystemReset()
void ETH_SendSystemReset (void )
Resets the system software.
| None. |
None. |
1.4.3.2.31 ETH_SetMAC()
void ETH_SetMAC (uint8_t * macAddr)
Sets the MAC address.
| *macAddr |
None. |
1.4.3.2.32 ETH_SetReadPtr()
void ETH_SetReadPtr (uint16_t rdptr)
Sets the read pointer to a specific address.
| rdptr |
Read pointer |
None. |
1.4.3.2.33 ETH_SetRxByteCount()
void ETH_SetRxByteCount (uint16_t count)
Sets the receiver's byte count.
| count |
byte count |
None. |
1.4.3.2.34 ETH_SetStatusVectorByteCount()
void ETH_SetStatusVectorByteCount (uint16_t bc)
Sets the Status Vector's byte count.
| bc |
Byte count |
None. |
1.4.3.2.35 ETH_TxComputeChecksum()
uint16_t ETH_TxComputeChecksum (uint16_t position, uint16_t length, uint16_t seed)
Calculates the hardware checksum of length bytes starting with the position.
| position | |
| length | |
| seed |
Checksum. |
1.4.3.2.36 ETH_TxReset()
void ETH_TxReset (void )
Resets the transmitter.
| None. |
None. |
1.4.3.2.37 ETH_Write16()
void ETH_Write16 (uint16_t data)
Writes two bytes into the TX buffer MAC in Network order.
| data |
None. |
1.4.3.2.38 ETH_Write24()
void ETH_Write24 (uint32_t data)
Writes three bytes into the TX buffer MAC in Network order.
| data |
None. |
1.4.3.2.39 ETH_Write32()
void ETH_Write32 (uint32_t data)
Writes four bytes into the TX buffer MAC in Network order.
| data |
None. |
1.4.3.2.40 ETH_Write8()
void ETH_Write8 (uint8_t data)
Writes one byte of data into the TX buffer MAC.
| data |
None. |
1.4.3.2.41 ETH_WriteBlock()
uint16_t ETH_WriteBlock (const char * data, uint16_t length)
Writes a block of data into the TX buffer MAC.
| *data | |
| length |
Length. |
1.4.3.2.42 ETH_WriteStart()
phy_error_msg ETH_WriteStart (const mac48Address_t * dest_mac, uint16_t type)
Starts a packet if the Ethernet transmitter is idle.
| *dest_mac | |
| type |
| PHY_SUCCESS |
Packet started |
| PHY_BUFFER_BUSY |
Buffer is busy |
| PHY_TX_LOGIC_NOT_IDLE |
Transmitter is busy |
1.4.3.2.43 ETH_WriteString()
uint16_t ETH_WriteString (const char * string)
Writes a string of data into the MAC.
| *string |
None. |
1.4.3.2.44 MAC_getAddress()
const mac48Address_t* MAC_getAddress (void )
Returns the MAC address of type mac48Address_t.
| None. |
MAC address. |
1.4.3.3 Enumeration Type Documentation
1.4.3.3.1 phy_error_msg
enum phy_error_msg
PHY status/errors.
| PHY_ERROR | |
| PHY_SUCCESS | |
| PHY_LINK_NOT_FOUND | |
| PHY_BUFFER_BUSY | |
| PHY_TX_LOGIC_NOT_IDLE | |
| PHY_TX_QUEUED | |
| PHY_DMA_TIMEOUT |
1.5 Class Documentation
1.5.1 eir_t Union Reference
ENC28J60 EIR register.
1.5.1.1 Detailed Description
ENC28J60 EIR register.
#include <enc28j60.h>
1.5.1.1.1 Public Attributes
1.5.1.2 Member Data Documentation
1.5.1.2.1 @1
struct { ... }
1.5.1.2.2 __pad0__
unsigned __pad0__
1.5.1.2.3 __pad1__
unsigned __pad1__
1.5.1.2.4 DMAIF
unsigned DMAIF
DMA Interrupt Flag bit
1.5.1.2.5 LINKIF
unsigned LINKIF
Link Change Interrupt Flag bit
1.5.1.2.6 PKTIF
unsigned PKTIF
Receive Packet Pending Interrupt Flag bit
1.5.1.2.7 RXERIF
unsigned RXERIF
Receive Error Interrupt Flag bit
1.5.1.2.8 TXERIF
unsigned TXERIF
Transmit Error Interrupt Flag bit
1.5.1.2.9 TXIF
unsigned TXIF
Transmit Interrupt Flag bit
1.5.1.2.10 val
char val
1.5.2 ethernetDriver_t Struct Reference
#include <physical_layer_interface.h>
1.5.2.1 Public Attributes
unsigned error: 1
unsigned pktReady: 1
unsigned up: 1
unsigned idle: 1
unsigned linkChange: 1
unsigned bufferBusy: 1
unsigned __pad0__: 3
uint16_t saveRDPT
uint16_t saveWRPT
1.5.2.2 Member Data Documentation
The documentation for this struct was generated from the following file:
source/
1.5.2.2.1 __pad0__
unsigned __pad0__
1.5.2.2.2 bufferBusy
unsigned bufferBusy
1.5.2.2.3 error
unsigned error
1.5.2.2.4 idle
unsigned idle
1.5.2.2.5 linkChange
unsigned linkChange
1.5.2.2.6 pktReady
unsigned pktReady
1.5.2.2.7 saveRDPT
uint16_t saveRDPT
1.5.2.2.8 saveWRPT
uint16_t saveWRPT
1.5.2.2.9 up
unsigned up
1.5.3 mac48Address_t Union Reference
MAC Address (48-bits).
1.5.3.1 Detailed Description
MAC Address (48-bits).
#include <physical_layer_interface.h>
1.5.3.1.1 Public Attributes
1.5.3.2 Member Data Documentation
The documentation for this union was generated from the following file:
source/
1.5.3.2.1 byte1
uint8_t byte1
1.5.3.2.2 byte2
uint8_t byte2
1.5.3.2.3 byte3
uint8_t byte3
1.5.3.2.4 byte4
uint8_t byte4
1.5.3.2.5 byte5
uint8_t byte5
1.5.3.2.6 byte6
uint8_t byte6
1.5.3.2.7 mac_array
uint8_t mac_array[6]
1.5.3.2.8 s
struct { ... } s
1.5.4 mac64Address_t Union Reference
MAC Address (64-bits).
1.5.4.1 Detailed Description
MAC Address (64-bits).
#include <physical_layer_interface.h>
1.5.4.1.1 Public Attributes
1.5.4.2 Member Data Documentation
The documentation for this union was generated from the following file:
source/
1.5.4.2.1 byte1
uint8_t byte1
1.5.4.2.2 byte2
uint8_t byte2
1.5.4.2.3 byte3
uint8_t byte3
1.5.4.2.4 byte4
uint8_t byte4
1.5.4.2.5 byte5
uint8_t byte5
1.5.4.2.6 byte6
uint8_t byte6
1.5.4.2.7 byte7
uint8_t byte7
1.5.4.2.8 byte8
uint8_t byte8
1.5.4.2.9 mac_array
uint8_t mac_array[8]
1.5.4.2.10 s
struct { ... } s
1.5.5 phstat2_t Union Reference
ENC28J60 PHSTAT2 register.
1.5.5.1 Detailed Description
ENC28J60 PHSTAT2 register.
#include <enc28j60.h>
1.5.5.1.1 Public Attributes
1.5.5.2 Member Data Documentation
1.5.5.2.1 @3
struct { ... }
1.5.5.2.2 __pad0__
unsigned __pad0__
1.5.5.2.3 __pad1__
unsigned __pad1__
1.5.5.2.4 __pad2__
unsigned __pad2__
1.5.5.2.5 COLSTAT
unsigned COLSTAT
PHY Collision Status bit
1.5.5.2.6 DPXSTAT
unsigned DPXSTAT
PHY Duplex Status bit
1.5.5.2.7 LSTAT
unsigned LSTAT
PHY Link Status bit (non-latching)
1.5.5.2.8 PLRITY
unsigned PLRITY
Polarity Status bit
1.5.5.2.9 RXSTAT
unsigned RXSTAT
PHY Receive Status bit
1.5.5.2.10 TXSTAT
unsigned TXSTAT
PHY Transmit Status bit
1.5.5.2.11 val
unsigned int val
1.5.6 receiveStatusVector_t Union Reference
ENC28J60 receive status vector.
1.5.6.1 Detailed Description
ENC28J60 receive status vector.
Receive status vector.
#include <enc28j60.h>
1.5.6.1.1 Public Attributes
uint8_t v [4]
struct {
uint16_t byteCount
unsigned long_drop_event: 1
unsigned __pad0__: 1
unsigned excessCarrierEvent: 1
unsigned __pad1__: 1
unsigned crcError: 1
unsigned lengthCheckError: 1
unsigned lengthLongError: 1
unsigned rxOK: 1
unsigned rxMulticast: 1
unsigned rxBroadcast: 1
unsigned dribbleNibble: 1
unsigned controlFrame: 1
unsigned pauseControlFrame: 1
unsigned unknownContrlFrame: 1
unsigned vlanTagPresent: 1
unsigned zero: 1
};
struct {
uint16_t byteCount
unsigned PreviouslyIgnored: 1
unsigned RXDCPreviouslySeen: 1
unsigned CarrierPreviouslySeen: 1
unsigned CodeViolation: 1
unsigned CRCError: 1
unsigned LengthCheckError: 1
unsigned LengthOutOfRange: 1
unsigned ReceiveOk: 1
unsigned Multicast: 1
unsigned Broadcast: 1
unsigned DribbleNibble: 1
unsigned ControlFrame: 1
unsigned PauseControlFrame: 1
unsigned UnsupportedOpcode: 1
unsigned VLANType: 1
unsigned RuntMatch: 1
unsigned filler: 1
unsigned HashMatch: 1
unsigned MagicPacketMatch: 1
unsigned PatternMatch: 1
unsigned UnicastMatch: 1
unsigned BroadcastMatch: 1
unsigned MulticastMatch: 1
unsigned ZeroH: 1
unsigned char Zero: 8
};
1.5.6.2 Member Data Documentation
The documentation for this union was generated from the following files:
source/
source/
1.5.6.2.1 @5
struct { ... }
1.5.6.2.2 @7
struct { ... }
1.5.6.2.3 __pad0__
unsigned __pad0__
1.5.6.2.4 __pad1__
unsigned __pad1__
1.5.6.2.5 Broadcast
unsigned Broadcast
Receive Broadcast Packet
1.5.6.2.6 BroadcastMatch
unsigned BroadcastMatch
Broadcast Filter Match
1.5.6.2.7 byteCount
uint16_t byteCount
Received Byte Count
1.5.6.2.8 CarrierPreviouslySeen
unsigned CarrierPreviouslySeen
Carrier Event Previously Seen
1.5.6.2.9 CodeViolation
unsigned CodeViolation
Code Violation
1.5.6.2.10 ControlFrame
unsigned ControlFrame
Receive Control Frame
1.5.6.2.11 controlFrame
unsigned controlFrame
Receive Control Frame
1.5.6.2.12 CRCError
unsigned CRCError
CRC Error
1.5.6.2.13 crcError
unsigned crcError
CRC Error
1.5.6.2.14 DribbleNibble
unsigned DribbleNibble
Dribble Nibble
1.5.6.2.15 dribbleNibble
unsigned dribbleNibble
Dribble Nibble
1.5.6.2.16 excessCarrierEvent
unsigned excessCarrierEvent
Carrier Event Previously Seen
1.5.6.2.17 filler
unsigned filler
Not-Me Filter Match
1.5.6.2.18 HashMatch
unsigned HashMatch
Hash Filter Match
1.5.6.2.19 LengthCheckError
unsigned LengthCheckError
Length Check Error
1.5.6.2.20 lengthCheckError
unsigned lengthCheckError
Length Check Error
1.5.6.2.21 lengthLongError
unsigned lengthLongError
Length Out of Range
1.5.6.2.22 LengthOutOfRange
unsigned LengthOutOfRange
Length Out of Range
1.5.6.2.23 long_drop_event
unsigned long_drop_event
Long Event/Drop Event
1.5.6.2.24 MagicPacketMatch
unsigned MagicPacketMatch
Magic Packet(TM) Filter Match
1.5.6.2.25 Multicast
unsigned Multicast
Receive Multicast Packet
1.5.6.2.26 MulticastMatch
unsigned MulticastMatch
Multicast Filter Match
1.5.6.2.27 PatternMatch
unsigned PatternMatch
Pattern Match Filter Match
1.5.6.2.28 PauseControlFrame
unsigned PauseControlFrame
Receive Pause Control Frame
1.5.6.2.29 pauseControlFrame
unsigned pauseControlFrame
Receive Pause Control Frame
1.5.6.2.30 PreviouslyIgnored
unsigned PreviouslyIgnored
Packet Previously Ignored
1.5.6.2.31 ReceiveOk
unsigned ReceiveOk
Received Ok
1.5.6.2.32 RuntMatch
unsigned RuntMatch
Runt Filter Match
1.5.6.2.33 rxBroadcast
unsigned rxBroadcast
Receive Broadcast Packet
1.5.6.2.34 RXDCPreviouslySeen
unsigned RXDCPreviouslySeen
RXDC Previously Seen
1.5.6.2.35 rxMulticast
unsigned rxMulticast
Receive Multicast Packet
1.5.6.2.36 rxOK
unsigned rxOK
Received Ok
1.5.6.2.37 UnicastMatch
unsigned UnicastMatch
Unicast Filter Match
1.5.6.2.38 unknownContrlFrame
unsigned unknownContrlFrame
Receive Unknown Opcode
1.5.6.2.39 UnsupportedOpcode
unsigned UnsupportedOpcode
Receive Unknown Opcode
1.5.6.2.40 v
uint8_t v
1.5.6.2.41 vlanTagPresent
unsigned vlanTagPresent
Receive VLAN Type Detected
1.5.6.2.42 VLANType
unsigned VLANType
Receive VLAN Type Detected
1.5.6.2.43 Zero
unsigned char Zero
1.5.6.2.44 zero
unsigned zero
Zero
1.5.6.2.45 ZeroH
unsigned ZeroH
Zero
1.5.7 txPacket_t Struct Reference
#include <physical_layer_interface.h>
1.5.7.1 Public Attributes
uint16_t flags
uint16_t packetStart
uint16_t packetEnd
void * prevPacket
void * nextPacket
1.5.7.2 Member Data Documentation
The documentation for this struct was generated from the following file:
source/
1.5.7.2.1 flags
uint16_t flags
1.5.7.2.2 nextPacket
void* nextPacket
1.5.7.2.3 packetEnd
uint16_t packetEnd
1.5.7.2.4 packetStart
uint16_t packetStart
1.5.7.2.5 prevPacket
void* prevPacket
1.6 File Documentation
1.6.1 source/enc28j60.c File Reference
This file provides the Ethernet driver API implementation for the ENC28J60 device.
#include <xc.h> #include <stdint.h> #include <stddef.h> #include "../enc28j60.h" #include "../../system/system.h" #include "../physical_layer_interface.h" #include "../../spi/spi_interface.h" #include "../../timer/delay.h"
1.6.1.1 Functions
const mac48Address_t * MAC_getAddress (void)
Returns the MAC address of type mac48Address_t.
phy_error_msg ETH_SendQueued (void)
Enqueues the latest written packet and starts the transmission of a queued packet.
phy_error_msg ETH_Shift_Tx_Packets (void)
Copies the queued packets to the TX Buffer start address using the DMA setup.
void ETH_PacketListReset (void)
Resets the Ethernet packet list.
txPacket_t * ETH_NewPacket (void)
Allocates a new packet element and links it to the chained list.
void ETH_RemovePacket (txPacket_t *pPacket)
Deallocates a packet element and unlinks it from the chained list.
static uint16_t ETH_ComputeChecksum (uint16_t len, uint16_t seed)
Calculates the checksum.
static uint8_t ENC28_Rcr8 (enc28j60_registers_t a)
Reads one byte from Special Function Register (SFR).
static uint16_t ENC28_Rcr16 (enc28j60_registers_t a)
Reads two bytes from SFRs.
static void ENC28_Wcr8 (enc28j60_registers_t a, uint8_t v)
Writes one byte to SFRs.
static void ENC28_Wcr16 (enc28j60_registers_t a, uint16_t v)
Writes two bytes to SFRs.
static void ENC28_Bfs (enc28j60_registers_t a, char bits)
Sets the SFR bit field.
static void ENC28_Bfc (enc28j60_registers_t a, char bits)
Clears the SFR bit field.
static uint16_t ENC28_PhyRead (enc28j60_phy_registers_t a)
Reads the Physical Layer (PHY) register.
static void ENC28_PhyWrite (enc28j60_phy_registers_t a, uint16_t d)
Writes the PHY register.
static void ENC28_BankSel (enc28j60_registers_t r)
Selects the bank.
static void ETH_CloseSPI (void)
Releases the Serial Peripheral Interface (SPI) bus.
static void ETH_OpenSPI (void)
Connects the SPI bus.
bool ETH_CheckLinkUp (void)
Checks for the link.
void ETH_Init (void)
Sets up the Ethernet and starts the execution. Initializes the TX/RX buffer, the MAC and the PHY.
void ETH_EventHandler (void)
Manages the MAC events. Can be used for polling or for new events in Interrupt Service Routine (ISR).
void ETH_NextPacketUpdate (void)
Updates the pointers for the next available RX packets. Retrieves information about the last received packet and the address of the next ones.
void ETH_ResetReceiver (void)
Resets the receiver buffer.
void ETH_SendSystemReset (void)
Resets the system software.
uint8_t ETH_Read8 (void)
Reads one byte of data from the RX buffer MAC.
uint16_t ETH_Read16 (void)
Reads two bytes of data from the RX buffer and returns them in host order.
uint32_t ETH_Read24 (void)
Reads three bytes of data from the RX buffer and returns them in host order.
uint32_t ETH_Read32 (void)
Reads four bytes of data from the RX buffer and returns them in host order.
uint16_t ETH_ReadBlock (void *buffer, uint16_t length)
Reads a block of data from the RX buffer MAC.
void ETH_Write8 (uint8_t data)
Writes one byte of data into the TX buffer MAC.
void ETH_Write16 (uint16_t data)
Writes two bytes into the TX buffer MAC in Network order.
void ETH_Write24 (uint32_t data)
Writes three bytes into the TX buffer MAC in Network order.
void ETH_Write32 (uint32_t data)
Writes four bytes into the TX buffer MAC in Network order.
uint16_t ETH_WriteString (const char *string)
Writes a string of data into the MAC.
uint16_t ETH_WriteBlock (const char *data, uint16_t length)
Writes a block of data into the TX buffer MAC.
uint16_t ETH_GetFreeTxBufferSize (void)
Returns the available space size in the Ethernet TX buffer.
phy_error_msg ETH_WriteStart (const mac48Address_t *dest_mac, uint16_t type)
Starts a packet if the Ethernet transmitter is idle.
phy_error_msg ETH_Send (void)
Sends the TX packet. Starts the transmission of packet or queues the packet that has been created.
void ETH_Dump (uint16_t length)
Drops the N bytes from a packet list when the data is lost. Clears a number of bytes (length) from the RX buffer.
void ETH_Flush (void)
Drops the rest of this packet and release the buffer. Clears all bytes from the RX buffer.
void ETH_Insert (char *data, uint16_t len, uint16_t offset)
Inserts N data bytes into a specific offset in the TX buffer/packet.
phy_error_msg ETH_Copy (uint16_t len)
Copies N bytes from the saved read location (RX buffer) into the current TX location (TX buffer) using the DMA set up. This is used for ICMP ECHO to eliminate the need to extract the arbitrary payload.
uint16_t ETH_TxComputeChecksum (uint16_t position, uint16_t length, uint16_t seed)
Calculates the hardware checksum of length bytes starting with the position.
uint16_t ETH_RxComputeChecksum (uint16_t len, uint16_t seed)
Calculates the RX software checksum.
void ETH_GetMAC (uint8_t *macAddr)
Reads the MAC address.
void ETH_SetMAC (uint8_t *macAddr)
Sets the MAC address.
void ETH_SaveRDPT (void)
Saves the receive pointer for copy.
uint16_t ETH_GetReadPtr (void)
Returns the value of the read pointer.
void ETH_SetReadPtr (uint16_t rdptr)
Sets the read pointer to a specific address.
void ETH_MoveBackReadPtr (uint16_t offset)
Moves back the read pointer.
void ETH_ResetReadPtr (void)
Resets the receive pointer to the Init.
uint16_t ETH_GetWritePtr (void)
Returns the value of the write pointer.
uint16_t ETH_GetRxByteCount (void)
Returns the receiver's byte count.
void ETH_SetRxByteCount (uint16_t count)
Sets the receiver's byte count.
void ETH_ResetByteCount (void)
Resets the driver's byte count.
uint16_t ETH_GetByteCount (void)
Returns the the driver's byte count.
void ETH_SaveWRPT (void)
Saves the write pointer for copy.
uint16_t ETH_ReadSavedWRPT (void)
Returns the saved write pointer.
uint16_t ETH_GetStatusVectorByteCount (void)
Returns the Status Vector's byte count.
void ETH_SetStatusVectorByteCount (uint16_t bc)
Sets the Status Vector's byte count.
void ETH_TxReset (void)
Resets the transmitter.
1.6.1.2 Macros
#define MAC_ADDRESS {0x02, 0x00, 0x00, 0x00, 0x00, 0x01}
#define BROADCAST_MAC {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
#define ETH_NCS_HIGH() do{ETH_CS_SetHigh();} while(0)
Sets Ethernet Chip Select to high.
#define ETH_NCS_LOW() do{ETH_CS_SetLow();} while(0)
Sets Ethernet Chip Select to low.
#define ETH_SPI_READ8() SPI1_Host.ByteExchange(0)
Reads the SPI byte.
#define ETH_SPI_WRITE8(a) SPI1_Host.ByteExchange(a)
Writes the SPI byte.
#define ETH_WRITE_IN_PROGRESS (0x0001 << 0)
Packet write in progress, not ready for transmit.
#define ETH_TX_QUEUED (0x0001 << 1)
Packet complete, in queue for transmit.
#define ETH_ALLOCATED (0x0001 << 2)
Flag for pool management. Set to either free or allocated.
#define RAMSIZE_ETH (0x1FFF)
#define MAX_TX_PACKET_SIZE (1518)
#define MIN_TX_PACKET_SIZE (64)
#define MAX_TX_PACKETS (20)
#define TX_STATUS_VECTOR_SIZE (7)
#define MIN_TX_PACKET (MIN_TX_PACKET_SIZE + TX_STATUS_VECTOR_SIZE)
#define TX_BUFFER_SIZE ((MAX_TX_PACKET_SIZE + TX_STATUS_VECTOR_SIZE) << 1)
#define TXSTART (RAMSIZE_ETH - TX_BUFFER_SIZE)
#define TXEND (RAMSIZE_ETH)
#define RXSTART (0)
#define TX_BUFFER_MID ((TXSTART) + ((TX_BUFFER_SIZE) >> 1))
#define SetBit(bitField, bitMask) do{ bitField = bitField | bitMask; } while(0)
#define ClearBit(bitField, bitMask) do{ bitField = bitField & (~bitMask); } while(0)
#define CheckBit(bitField, bitMask) (bool)(bitField & bitMask)
1.6.1.3 Variables
volatile ethernetDriver_t ethData
const mac48Address_t broadcastMAC = {BROADCAST_MAC}
const mac48Address_t * eth_MAC
static uint16_t nextPacketPointer
uint8_t ethListSize
static txPacket_t txData [MAX_TX_PACKETS]
static txPacket_t * pHead
static txPacket_t * pTail
uint16_t TXPacketSize
1.6.1.4 Detailed Description
This file provides the Ethernet driver API implementation for the ENC28J60 device.
ENC28J60 Ethernet Driver Source File
1.6.1.5 Macro Definition Documentation
1.6.1.5.1 BROADCAST_MAC
#define BROADCAST_MAC {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
1.6.1.5.2 CheckBit
#define CheckBit( bitField, bitMask) (bool)(bitField & bitMask)
1.6.1.5.3 ClearBit
#define ClearBit( bitField, bitMask) do{ bitField = bitField & (~bitMask); } while(0)
1.6.1.5.4 MAC_ADDRESS
#define MAC_ADDRESS {0x02, 0x00, 0x00, 0x00, 0x00, 0x01}
1.6.1.5.5 MAX_TX_PACKET_SIZE
#define MAX_TX_PACKET_SIZE (1518)
1.6.1.5.6 MAX_TX_PACKETS
#define MAX_TX_PACKETS (20)
1.6.1.5.7 MIN_TX_PACKET
#define MIN_TX_PACKET (MIN_TX_PACKET_SIZE + TX_STATUS_VECTOR_SIZE)
1.6.1.5.8 MIN_TX_PACKET_SIZE
#define MIN_TX_PACKET_SIZE (64)
1.6.1.5.9 RAMSIZE_ETH
#define RAMSIZE_ETH (0x1FFF)
1.6.1.5.10 RXEND
#define RXEND (TXSTART - 2)
1.6.1.5.11 RXSTART
#define RXSTART (0)
1.6.1.5.12 SetBit
#define SetBit( bitField, bitMask) do{ bitField = bitField | bitMask; } while(0)
1.6.1.5.13 TX_BUFFER_MID
#define TX_BUFFER_MID ((TXSTART) + ((TX_BUFFER_SIZE) >> 1))
1.6.1.5.14 TX_BUFFER_SIZE
#define TX_BUFFER_SIZE ((MAX_TX_PACKET_SIZE + TX_STATUS_VECTOR_SIZE) << 1)
1.6.1.5.15 TX_STATUS_VECTOR_SIZE
#define TX_STATUS_VECTOR_SIZE (7)
1.6.1.5.16 TXEND
#define TXEND (RAMSIZE_ETH)
1.6.1.5.17 TXSTART
#define TXSTART (RAMSIZE_ETH - TX_BUFFER_SIZE)
1.6.1.6 Variable Documentation
1.6.1.6.1 broadcastMAC
const mac48Address_t broadcastMAC = {BROADCAST_MAC}
1.6.1.6.2 eth_MAC
const mac48Address_t* eth_MAC
1.6.1.6.3 ethData
volatile ethernetDriver_t ethData
1.6.1.6.4 ethListSize
uint8_t ethListSize
1.6.1.6.5 lastBank
sfr_bank_t lastBank
1.6.1.6.6 macAddress
mac48Address_t macAddress = {MAC_ADDRESS}
1.6.1.6.7 nextPacketPointer
uint16_t nextPacketPointer[static]
1.6.1.6.8 pHead
txPacket_t* pHead[static]
1.6.1.6.9 pTail
txPacket_t* pTail[static]
1.6.1.6.10 rxPacketStatusVector
receiveStatusVector_t rxPacketStatusVector[static]
1.6.1.6.11 txData
txPacket_t txData[MAX_TX_PACKETS][static]
1.6.1.6.12 TXPacketSize
uint16_t TXPacketSize
1.6.2 source/enc28j60.h File Reference
1.6.2.1 Data structures
union eir_t
ENC28J60 EIR register.
union phstat2_t
ENC28J60 PHSTAT2 register.
union receiveStatusVector_t
ENC28J60 receive status vector.
1.6.2.2 Macros
#define SFR_BANK0 0x00
#define SFR_BANK1 0x40
#define SFR_BANK2 0x80
#define SFR_BANK3 0xC0
#define SFR_COMMON 0xE0
#define BANK_MASK 0xE0
#define SFR_MASK 0x1F
#define byteSwap16(a) ((((uint16_t)a & (uint16_t)0xFF00) >> 8) | (((uint16_t)a & (uint16_t)0x00FF) << 8))
#define byteReverse32(a)
#define byteReverse24(a) (((((uint32_t)a & (uint32_t)0x00FF00) >> 8) | (((uint32_t)a & (uint32_t)0x0000FF) << 8)) << 8 | (uint32_t)a >> 0x10)
#define htons(a) byteSwap16(a)
#define ntohs(a) byteSwap16(a)
#define htonl(a) byteReverse32(a)
#define ntohl(a) byteReverse32(a)
#define convert_hton24(a) byteReverse24(a)
1.6.2.3 Enumerations
enum spi_inst_t { rcr_inst = 0x00, rbm_inst = 0x3A, wcr_inst = 0x40, wbm_inst = 0x7A, bfs_inst = 0x80, bfc_inst = 0xa0, src_inst = 0xFF }
SPI instructions.
enum sfr_bank_t { sfr_bank0 = SFR_BANK0, sfr_bank1 = SFR_BANK1, sfr_bank2 = SFR_BANK2, sfr_bank3 = SFR_BANK3, sfr_common = SFR_COMMON, sfr_bank0 = SFR_BANK0, sfr_bank1 = SFR_BANK1, sfr_bank2 = SFR_BANK2, sfr_bank3 = SFR_BANK3, sfr_common = SFR_COMMON }
SFR banks.
enum enc28j60_registers_t { J60_ERDPTL = (SFR_BANK0 | 0x00), J60_ERDPTH = (SFR_BANK0 | 0x01), J60_EWRPTL = (SFR_BANK0 | 0x02), J60_EWRPTH = (SFR_BANK0 | 0x03), J60_ETXSTL = (SFR_BANK0 | 0x04), J60_ETXSTH = (SFR_BANK0 | 0x05), J60_ETXNDL = (SFR_BANK0 | 0x06), J60_ETXNDH = (SFR_BANK0 | 0x07), J60_ERXSTL = (SFR_BANK0 | 0x08), J60_ERXSTH = (SFR_BANK0 | 0x09), J60_ERXNDL = (SFR_BANK0 | 0x0A), J60_ERXNDH = (SFR_BANK0 | 0x0B), J60_ERXRDPTL = (SFR_BANK0 | 0x0C), J60_ERXRDPTH = (SFR_BANK0 | 0x0D), J60_ERXWRPTL = (SFR_BANK0 | 0x0E), J60_ERXWRPTH = (SFR_BANK0 | 0x0F), J60_EDMASTL = (SFR_BANK0 | 0x10), J60_EDMASTH = (SFR_BANK0 | 0x11), J60_EDMANDL = (SFR_BANK0 | 0x12), J60_EDMANDH = (SFR_BANK0 | 0x13), J60_EDMADSTL = (SFR_BANK0 | 0x14), J60_EDMADSTH = (SFR_BANK0 | 0x15), J60_EDMACSL = (SFR_BANK0 | 0x16), J60_EDMACSH = (SFR_BANK0 | 0x17), RSRV_018 = (SFR_BANK0 | 0x18), RSRV_019 = (SFR_BANK0 | 0x19), RSRV_01A = (SFR_BANK0 | 0x1A), J60_EHT0 = (SFR_BANK1 | 0x00), J60_EHT1 = (SFR_BANK1 | 0x01), J60_EHT2 = (SFR_BANK1 | 0x02), J60_EHT3 = (SFR_BANK1 | 0x03), J60_EHT4 = (SFR_BANK1 | 0x04), J60_EHT5 = (SFR_BANK1 | 0x05), J60_EHT6 = (SFR_BANK1 | 0x06), J60_EHT7 = (SFR_BANK1 | 0x07), J60_EPMM0 = (SFR_BANK1 | 0x08), J60_EPMM1 = (SFR_BANK1 | 0x09), J60_EPMM2 = (SFR_BANK1 | 0x0A), J60_EPMM3 = (SFR_BANK1 | 0x0B), J60_EPMM4 = (SFR_BANK1 | 0x0C), J60_EPMM5 = (SFR_BANK1 | 0x0D), J60_EPMM6 = (SFR_BANK1 | 0x0E), J60_EPMM7 = (SFR_BANK1 | 0x0F), J60_EPMCSL = (SFR_BANK1 | 0x10), J60_EPMCSH = (SFR_BANK1 | 0x11), RSRV_112 = (SFR_BANK1 | 0x12), RSRV_113 = (SFR_BANK1 | 0x13), J60_EPMOL = (SFR_BANK1 | 0x14), J60_EPMOH = (SFR_BANK1 | 0x15), RSRV_116 = (SFR_BANK1 | 0x16), RSRV_117 = (SFR_BANK1 | 0x17), J60_ERXFCON = (SFR_BANK1 | 0x18), J60_EPKTCNT = (SFR_BANK1 | 0x19), RSRV_11A = (SFR_BANK1 | 0x1A), J60_MACON1 = (SFR_BANK2 | 0x00), RSRV_201 = (SFR_BANK2 | 0x01), J60_MACON3 = (SFR_BANK2 | 0x02), J60_MACON4 = (SFR_BANK2 | 0x03), J60_MABBIPG = (SFR_BANK2 | 0x04), RSRV_205 = (SFR_BANK2 | 0x05), J60_MAIPGL = (SFR_BANK2 | 0x06), J60_MAIPGH = (SFR_BANK2 | 0x07), J60_MACLCON1 = (SFR_BANK2 | 0x08), J60_MACLCON2 = (SFR_BANK2 | 0x09), J60_MAMXFLL = (SFR_BANK2 | 0x0A), J60_MAMXFLH = (SFR_BANK2 | 0x0B), RSRV_20C = (SFR_BANK2 | 0x0C), RSRV_20D = (SFR_BANK2 | 0x0D), RSRV_20E = (SFR_BANK2 | 0x0E), RSRV_20F = (SFR_BANK2 | 0x0F), RSRV_210 = (SFR_BANK2 | 0x10), RSRV_211 = (SFR_BANK2 | 0x11), J60_MICMD = (SFR_BANK2 | 0x12), RSRV_213 = (SFR_BANK2 | 0x13), J60_MIREGADR = (SFR_BANK2 | 0x14), RSRV_215 = (SFR_BANK2 | 0x15), J60_MIWRL = (SFR_BANK2 | 0x16), J60_MIWRH = (SFR_BANK2 | 0x17), J60_MIRDL = (SFR_BANK2 | 0x18), J60_MIRDH = (SFR_BANK2 | 0x19), RSRV_21A = (SFR_BANK2 | 0x1A), J60_MAADR5 = (SFR_BANK3 | 0x00), J60_MAADR6 = (SFR_BANK3 | 0x01), J60_MAADR3 = (SFR_BANK3 | 0x02), J60_MAADR4 = (SFR_BANK3 | 0x03), J60_MAADR1 = (SFR_BANK3 | 0x04), J60_MAADR2 = (SFR_BANK3 | 0x05), J60_EBSTSD = (SFR_BANK3 | 0x06), J60_EBSTCON = (SFR_BANK3 | 0x07), J60_EBSTCSL = (SFR_BANK3 | 0x08), J60_EBSTCSH = (SFR_BANK3 | 0x09), J60_MISTAT = (SFR_BANK3 | 0x0A), RSRV_30B = (SFR_BANK3 | 0x0B), RSRV_30C = (SFR_BANK3 | 0x0C), RSRV_30D = (SFR_BANK3 | 0x0D), RSRV_30E = (SFR_BANK3 | 0x0E), RSRV_30F = (SFR_BANK3 | 0x0F), RSRV_310 = (SFR_BANK3 | 0x10), RSRV_311 = (SFR_BANK3 | 0x11), J60_EREVID = (SFR_BANK3 | 0x12), RSRV_313 = (SFR_BANK3 | 0x13), RSRV_314 = (SFR_BANK3 | 0x14), J60_ECOCON = (SFR_BANK3 | 0x15), RSRV_316 = (SFR_BANK3 | 0x16), J60_EFLOCON = (SFR_BANK3 | 0x17), J60_EPAUSL = (SFR_BANK3 | 0x18), J60_EPAUSH = (SFR_BANK3 | 0x19), RSRV_31A = (SFR_BANK3 | 0x1A), J60_EIE = (SFR_COMMON | 0x1B), J60_EIR = (SFR_COMMON | 0x1C), J60_ESTAT = (SFR_COMMON | 0x1D), J60_ECON2 = (SFR_COMMON | 0x1E), J60_ECON1 = (SFR_COMMON | 0x1F) }
ENC28J60 registers.
enum enc28j60_phy_registers_t { J60_PHCON1 = 0x00, J60_PHSTAT1 = 0x01, J60_PHID1 = 0x02, J60_PHID2 = 0x03, J60_PHCON2 = 0x10, J60_PHSTAT2 = 0x11, J60_PHIE = 0x12, J60_PHIR = 0x13, J60_PHLCON = 0x14 }
ENC28J60 PHY register addresses.
1.6.2.4 Variables
uint8_t Control_Byte
ENC28J60 Control Byte.
1.6.2.5 Detailed Description
ENC28J60 Ethernet Driver Header File
1.6.2.6 Macro Definition Documentation
1.6.2.6.1 BANK_MASK
#define BANK_MASK 0xE0
1.6.2.6.2 byteReverse24
#define byteReverse24( a) (((((uint32_t)a & (uint32_t)0x00FF00) >> 8) | (((uint32_t)a & (uint32_t)0x0000FF) << 8)) << 8 | (uint32_t)a >> 0x10)
1.6.2.6.3 byteReverse32
#define byteReverse32( a)
Value:
((((uint32_t)a & (uint32_t)0xff000000) >> 24) | \ (((uint32_t)a & (uint32_t)0x00ff0000) >> 8) | \ (((uint32_t)a & (uint32_t)0x0000ff00) << 8) | \ (((uint32_t)a & (uint32_t)0x000000ff) << 24))
1.6.2.6.4 byteSwap16
#define byteSwap16( a) ((((uint16_t)a & (uint16_t)0xFF00) >> 8) | (((uint16_t)a & (uint16_t)0x00FF) << 8))
1.6.2.6.5 convert_hton24
#define convert_hton24( a) byteReverse24(a)
1.6.2.6.6 htonl
#define htonl( a) byteReverse32(a)
1.6.2.6.7 htons
#define htons( a) byteSwap16(a)
1.6.2.6.8 ntohl
#define ntohl( a) byteReverse32(a)
1.6.2.6.9 ntohs
#define ntohs( a) byteSwap16(a)
1.6.2.6.10 SFR_BANK0
#define SFR_BANK0 0x00
1.6.2.6.11 SFR_BANK1
#define SFR_BANK1 0x40
1.6.2.6.12 SFR_BANK2
#define SFR_BANK2 0x80
1.6.2.6.13 SFR_BANK3
#define SFR_BANK3 0xC0
1.6.2.6.14 SFR_COMMON
#define SFR_COMMON 0xE0
1.6.2.6.15 SFR_MASK
#define SFR_MASK 0x1F
1.6.3 source/encx24j600_driver.c File Reference
This file provides the Ethernet driver API implementation for the ENCx24J600 family devices.
#include <xc.h> #include <stdint.h> #include <stdbool.h> #include <stdio.h> #include "../../system/system.h" #include "../physical_layer_interface.h" #include "../encx24j600_spi.h" #include "../../spi/spi_interface.h" #include "../../timer/delay.h"
1.6.3.1 Functions
phy_error_msg ETH_SendQueued (void)
Enqueues the latest written packet and starts the transmission of a queued packet.
phy_error_msg ETH_Shift_Tx_Packets (void)
Copies all the queued packets to the TX Buffer start address using the DMA setup.
void ETH_PacketListReset (void)
Resets the Ethernet packet list.
txPacket_t * ETH_NewPacket (void)
Allocates a new packet element and links it to the chained list.
void ETH_RemovePacket (txPacket_t *pPacket)
Deallocates a packet element and unlinks it from the chained list.
static uint16_t ETH_DMAComputeChecksum (uint16_t rxPtr, uint16_t len, uint16_t seed)
Calculates the checksum.
static void ETH_CloseSPI (void)
Releases the Serial Peripheral Interface (SPI) bus.
static void ETH_OpenSPI (void)
Connects the SPI bus.
static void waitForDMA (void)
Waits for the DMA.
static uint32_t ETH_readLinkStatus (void)
Checks for the link status.
const mac48Address_t * MAC_getAddress (void)
Returns the MAC address of type mac48Address_t.
void ETH_SendSystemReset (void)
Resets the system software.
void ETH_Init (void)
Sets up the Ethernet and starts the execution. Initializes the TX/RX buffer, the MAC and the PHY.
bool ETH_CheckLinkUp (void)
Checks for the link.
void ETH_EventHandler (void)
Manages the MAC events. Can be used for polling or for new events in Interrupt Service Routine (ISR).
void ETH_NextPacketUpdate (void)
Updates the pointers for the next available RX packets. Retrieves information about the last received packet and the address of the next ones.
void ETH_ResetReceiver (void)
Resets the receiver buffer.
void ETH_Dump (uint16_t length)
Drops the N bytes from a packet list when the data is lost. Clears a number of bytes (length) from the RX buffer.
void ETH_Flush (void)
Drops the rest of this packet and release the buffer. Clears all bytes from the RX buffer.
phy_error_msg ETH_WriteStart (const mac48Address_t *dest_mac, uint16_t type)
Starts a packet if the Ethernet transmitter is idle.
phy_error_msg ETH_Send (void)
Sends the TX packet. Starts the transmission of packet or queues the packet that has been created.
phy_error_msg ETH_Copy (uint16_t len)
Copies N bytes from the saved read location (RX buffer) into the current TX location (TX buffer) using the DMA set up. This is used for ICMP ECHO to eliminate the need to extract the arbitrary payload.
void ETH_GetMAC (uint8_t *macAddr)
Reads the MAC address.
void ETH_SetMAC (uint8_t *macAddr)
Sets the MAC address.
uint16_t ETH_TxComputeChecksum (uint16_t position, uint16_t length, uint16_t seed)
Calculates the hardware checksum of length bytes starting with the position.
uint16_t ETH_RxComputeChecksum (uint16_t len, uint16_t seed)
Calculates the RX software checksum.
void ETH_SaveRDPT (void)
Saves the receive pointer for copy.
void ETH_ResetByteCount (void)
Resets the driver's byte count.
uint16_t ETH_GetByteCount (void)
Returns the the driver's byte count.
uint16_t ETH_GetReadPtr (void)
Returns the value of the read pointer.
void ETH_SetReadPtr (uint16_t rdptr)
Sets the read pointer to a specific address.
void ETH_MoveBackReadPtr (uint16_t offset)
Moves back the read pointer.
void ETH_ResetReadPtr (void)
Resets the receive pointer to the Init.
uint16_t ETH_GetWritePtr (void)
Returns the value of the write pointer.
uint16_t ETH_GetRxByteCount (void)
Returns the receiver's byte count.
void ETH_SetRxByteCount (uint16_t count)
Sets the receiver's byte count.
void ETH_SaveWRPT (void)
Saves the write pointer for copy.
uint16_t ETH_ReadSavedWRPT (void)
Returns the saved write pointer.
uint16_t ETH_GetStatusVectorByteCount (void)
Returns the Status Vector's byte count.
void ETH_SetStatusVectorByteCount (uint16_t bc)
Sets the Status Vector's byte count.
void ETH_TxReset (void)
Resets the transmitter.
1.6.3.2 Macros
#define ETH_WRITE_IN_PROGRESS (0x0001 << 0)
Packet write in progress, not ready for transmit.
#define ETH_TX_QUEUED (0x0001 << 1)
Packet in queue for transmit.
#define ETH_ALLOCATED (0x0001 << 2)
Flag for pool management. Set to either free or allocated.
#define MAX_TX_PACKET_SIZE (1518)
#define MIN_TX_PACKET_SIZE (64)
#define MAX_TX_PACKETS (20)
#define MIN_TX_PACKET (MIN_TX_PACKET_SIZE)
#define TX_BUFFER_SIZE (TXEND - TXSTART)
#define TX_BUFFER_MID ((TXSTART + TXEND) >> 1)
#define SetBit(bitField, bitMask) do{bitField = bitField | bitMask; } while(0)
#define ClearBit(bitField, bitMask) do{bitField = bitField & (~bitMask); } while(0)
#define CheckBit(bitField, bitMask) (bool)(bitField & bitMask)
#define MAC_ADDRESS {0x02, 0x00, 0x00, 0x00, 0x00, 0x01}
#define BROADCAST_MAC {0xff,0xff,0xff,0xff,0xff,0xff}
1.6.3.3 Variables
const mac48Address_t broadcastMAC = {BROADCAST_MAC}
volatile ethernetDriver_t ethData
uint8_t ethListSize
static txPacket_t txData [MAX_TX_PACKETS]
static txPacket_t * pHead
static txPacket_t * pTail
static uint16_t nextPacketPointer
1.6.3.4 Detailed Description
This file provides the Ethernet driver API implementation for the ENCx24J600 family devices.
ENCx24J600 Ethernet Driver source file
1.6.3.5 Macro Definition Documentation
1.6.3.5.1 BROADCAST_MAC
#define BROADCAST_MAC {0xff,0xff,0xff,0xff,0xff,0xff}
1.6.3.5.2 CheckBit
#define CheckBit( bitField, bitMask) (bool)(bitField & bitMask)
1.6.3.5.3 ClearBit
#define ClearBit( bitField, bitMask) do{bitField = bitField & (~bitMask); } while(0)
1.6.3.5.4 MAC_ADDRESS
#define MAC_ADDRESS {0x02, 0x00, 0x00, 0x00, 0x00, 0x01}
1.6.3.5.5 MAX_TX_PACKET_SIZE
#define MAX_TX_PACKET_SIZE (1518)
1.6.3.5.6 MAX_TX_PACKETS
#define MAX_TX_PACKETS (20)
1.6.3.5.7 MIN_TX_PACKET
#define MIN_TX_PACKET (MIN_TX_PACKET_SIZE)
1.6.3.5.8 MIN_TX_PACKET_SIZE
#define MIN_TX_PACKET_SIZE (64)
1.6.3.5.9 SetBit
#define SetBit( bitField, bitMask) do{bitField = bitField | bitMask; } while(0)
1.6.3.5.10 TX_BUFFER_MID
#define TX_BUFFER_MID ((TXSTART + TXEND) >> 1)
1.6.3.5.11 TX_BUFFER_SIZE
#define TX_BUFFER_SIZE (TXEND - TXSTART)
1.6.3.6 Variable Documentation
1.6.3.6.1 broadcastMAC
const mac48Address_t broadcastMAC = {BROADCAST_MAC}
1.6.3.6.2 ethData
volatile ethernetDriver_t ethData
1.6.3.6.3 ethListSize
uint8_t ethListSize
1.6.3.6.4 ethMAC
mac48Address_t ethMAC
1.6.3.6.5 macAddress
mac48Address_t macAddress = {MAC_ADDRESS}
1.6.3.6.6 nextPacketPointer
uint16_t nextPacketPointer[static]
1.6.3.6.7 pHead
txPacket_t* pHead[static]
1.6.3.6.8 pTail
txPacket_t* pTail[static]
1.6.3.6.9 txData
txPacket_t txData[MAX_TX_PACKETS][static]
1.6.4 source/encx24j600_spi.c File Reference
This file provides the SPI Interface Ethernet driver API implementation for the ENCx24J600 family devices.
#include <stdint.h> #include <stdbool.h> #include <stdio.h> #include "../../system/system.h" #include "../encx24j600_spi.h" #include "../physical_layer_interface.h"
1.6.4.1 Functions
static void ENCx24_BankselSPI (encX24J600_registers_t a)
Selects the SPI bank.
uint16_t ENCx24_Read (encX24J600_registers_t a)
Reads from Special Function Register (SFR).
void ENCx24_Write (encX24J600_registers_t a, uint16_t data)
Writes to SFRs.
void ENCx24_BFS (encX24J600_registers_t a, uint16_t bitMask)
Sets the SFR bit field.
void ENCx24_BFC (encX24J600_registers_t a, uint16_t bitMask)
Clears the SFR bit field.
uint16_t ENCx24_PhyRead (encX24J600_phy_registers_t a)
Reads the PHY register.
void ENCx24_PHYWrite (encX24J600_phy_registers_t a, uint16_t data)
Writes the PHY register.
uint8_t ETH_Read8 (void)
Reads one byte of data from the RX buffer MAC.
uint16_t ETH_Read16 (void)
Reads two bytes of data from the RX buffer and returns them in host order.
uint32_t ETH_Read32 (void)
Reads four bytes of data from the RX buffer and returns them in host order.
uint16_t ETH_ReadBlock (void *buffer, uint16_t length)
Reads a block of data from the RX buffer MAC.
void ETH_Write8 (uint8_t data)
Writes one byte of data into the TX buffer MAC.
void ETH_Write16 (uint16_t data)
Writes two bytes into the TX buffer MAC in Network order.
void ETH_Write24 (uint32_t data)
Writes three bytes into the TX buffer MAC in Network order.
void ETH_Write32 (uint32_t data)
Writes four bytes into the TX buffer MAC in Network order.
uint16_t ETH_WriteString (const char *string)
Writes a string of data into the MAC.
uint16_t ETH_WriteBlock (const char *data, uint16_t length)
Writes a block of data into the TX buffer MAC.
void ETH_Insert (char *data, uint16_t len, uint16_t offset)
Inserts N data bytes into a specific offset in the TX buffer/packet.
void ETH_Set_TXRTS (void)
Packet transmission request.
void ETH_SetPktDec (void)
Decrements packet count.
void ETH_SetRXptr (uint16_t address)
RX packet read pointer.
uint8_t ETH_EdataRead (encX24J600_registers_t a)
Reads the 8-bit data from the ENCx24J600 register (work around for Errata).
void ETH_MACWrite8 (encX24J600_registers_t a, uint8_t data)
Writes the 8-bit MAC-related data to ENCx24J600 registers.
uint8_t ETH_MACRead8 (encX24J600_registers_t a)
Reads the 8-bit MAC-related data from ENCx24J600 registers.
1.6.4.2 Variables
uint16_t TXPacketSize
receiveStatusVector_t rxPacketStatusVector = {{0, 0, 0, 0, 0, 0}}
1.6.4.3 Detailed Description
This file provides the SPI Interface Ethernet driver API implementation for the ENCx24J600 family devices.
ENCx24J600 SPI Driver File
1.6.4.4 Variable Documentation
1.6.4.4.1 last_bank
sfr_bank_t last_bank
1.6.4.4.2 rxPacketStatusVector
receiveStatusVector_t rxPacketStatusVector = {{0, 0, 0, 0, 0, 0}}
1.6.4.4.3 TXPacketSize
uint16_t TXPacketSize
1.6.5 source/encx24j600_spi.h File Reference
This header file provides the serial interface API for the ENCx24J600 devices.
#include "encx24j600_types.h" #include "../system/system.h" #include "../spi/spi_interface.h"
1.6.5.1 Data structures
union receiveStatusVector_t
ENC28J60 receive status vector.
1.6.5.2 Functions
uint16_t ENCx24_Read (encX24J600_registers_t a)
Reads from Special Function Register (SFR).
uint8_t ETH_EdataRead (encX24J600_registers_t a)
Reads the 8-bit data from the ENCx24J600 register (work around for Errata).
void ENCx24_Write (encX24J600_registers_t a, uint16_t data)
Writes to SFRs.
void ENCx24_BFS (encX24J600_registers_t a, uint16_t bitMask)
Sets the SFR bit field.
void ENCx24_BFC (encX24J600_registers_t a, uint16_t bitMask)
Clears the SFR bit field.
uint16_t ENCx24_PhyRead (encX24J600_phy_registers_t a)
Reads the PHY register.
void ENCx24_PHYWrite (encX24J600_phy_registers_t a, uint16_t data)
Writes the PHY register.
uint8_t ETH_MACRead8 (encX24J600_registers_t a)
Reads the 8-bit MAC-related data from ENCx24J600 registers.
void ETH_MACWrite8 (encX24J600_registers_t a, uint8_t data)
Writes the 8-bit MAC-related data to ENCx24J600 registers.
void ETH_SetPktDec (void)
Decrements packet count.
void ETH_SetRXptr (uint16_t address)
RX packet read pointer.
void ETH_Set_TXRTS (void)
Packet transmission request.
1.6.5.3 Macros
#define byteSwap16(a) ((((uint16_t)a & (uint16_t)0xFF00) >> 8) | (((uint16_t)a & (uint16_t)0x00FF) << 8))
#define byteReverse32(a)
#define byteReverse24(a) (((((uint32_t)a & (uint32_t)0x00FF00) >> 8) | (((uint32_t)a & (uint32_t)0x0000FF) << 8)) << 8 | (uint32_t)a >> 0x10)
#define htons(a) byteSwap16(a)
#define ntohs(a) byteSwap16(a)
#define htonl(a) byteReverse32(a)
#define ntohl(a) byteReverse32(a)
#define convert_hton24(a) byteReverse24(a)
#define ETH_NCS_HIGH() do{ETH_CS_SetHigh();} while(0)
Sets Ethernet Chip Select to high.
#define ETH_NCS_LOW() do{ETH_CS_SetLow();} while(0)
Sets Ethernet Chip Select to low.
#define ETH_READ8() SPI1_Host.ByteExchange(0)
Reads the Serial Peripheral Interface (SPI) byte.
#define ETH_WRITE8(a) SPI1_Host.ByteExchange(a)
Packet write in progress, not ready for transmit.
#define SFR_BANK0 0x00
#define SFR_BANK1 0x20
#define SFR_BANK2 0x40
#define SFR_BANK3 0x60
#define UNBANKED 0X80
#define SFR_COMMON 0xE0
#define BANK_MASK 0xE0
#define SFR_MASK 0x1F
1.6.5.4 Enumerations
enum sfr_bank_t { sfr_bank0 = SFR_BANK0, sfr_bank1 = SFR_BANK1, sfr_bank2 = SFR_BANK2, sfr_bank3 = SFR_BANK3, sfr_common = SFR_COMMON, sfr_bank0 = SFR_BANK0, sfr_bank1 = SFR_BANK1, sfr_bank2 = SFR_BANK2, sfr_bank3 = SFR_BANK3, sfr_common = SFR_COMMON }
enum encX24J600_registers_t { XJ600_ETXSTL = (SFR_BANK0 | 0x00), XJ600_ETXLENL = (SFR_BANK0 | 0x02), XJ600_ERXSTL = (SFR_BANK0 | 0x04), XJ600_ERXTAILL = (SFR_BANK0 | 0x06), XJ600_ERXHEADL = (SFR_BANK0 | 0x08), XJ600_EDMASTL = (SFR_BANK0 | 0x0A), XJ600_EDMALENL = (SFR_BANK0 | 0x0C), XJ600_EDMADSTL = (SFR_BANK0 | 0x0E), XJ600_EDMACSL = (SFR_BANK0 | 0x10), XJ600_ETXSTATL = (SFR_BANK0 | 0x12), XJ600_ETXWIREL = (SFR_BANK0 | 0x14), XJ600_EHT1L = (SFR_BANK1 | 0x00), XJ600_EHT2L = (SFR_BANK1 | 0x02), XJ600_EHT3L = (SFR_BANK1 | 0x04), XJ600_EHT4L = (SFR_BANK1 | 0x06), XJ600_EPMM1L = (SFR_BANK1 | 0x08), XJ600_EPMM2L = (SFR_BANK1 | 0x0A), XJ600_EPMM3L = (SFR_BANK1 | 0x0C), XJ600_EPMM4L = (SFR_BANK1 | 0x0E), XJ600_EPMCSL = (SFR_BANK1 | 0x10), XJ600_EPMOL = (SFR_BANK1 | 0x12), XJ600_ERXFCONL = (SFR_BANK1 | 0x14), XJ600_MACON1L = (SFR_BANK2 | 0x00), XJ600_MACON2L = (SFR_BANK2 | 0x02), XJ600_MABBIPGL = (SFR_BANK2 | 0x04), XJ600_MAIPGL = (SFR_BANK2 | 0x06), XJ600_MACLCONL = (SFR_BANK2 | 0x08), XJ600_MAMXFLL = (SFR_BANK2 | 0x0A), XJ600_MICMDL = (SFR_BANK2 | 0x12), XJ600_MIREGADRL = (SFR_BANK2 | 0x14), XJ600_MAADR3L = (SFR_BANK3 | 0x00), XJ600_MAADR3H = (SFR_BANK3 | 0x01), XJ600_MAADR2L = (SFR_BANK3 | 0x02), XJ600_MAADR2H = (SFR_BANK3 | 0x03), XJ600_MAADR1L = (SFR_BANK3 | 0x04), XJ600_MAADR1H = (SFR_BANK3 | 0x05), XJ600_MIWRL = (SFR_BANK3 | 0x06), XJ600_MIRDL = (SFR_BANK3 | 0x08), XJ600_MISTATL = (SFR_BANK3 | 0x0A), XJ600_EPAUSL = (SFR_BANK3 | 0x0C), XJ600_ECON2L = (SFR_BANK3 | 0x0E), XJ600_ERXWML = (SFR_BANK3 | 0x10), XJ600_EIEL = (SFR_BANK3 | 0x12), XJ600_EIDLEDL = (SFR_BANK3 | 0x14), XJ600_EGPDATAL = (UNBANKED | 0x00), XJ600_ERXDATAL = (UNBANKED | 0x02), XJ600_EUDADATAL = (UNBANKED | 0x04), XJ600_EGPRDPTL = (UNBANKED | 0x06), XJ600_EGPWRPTL = (UNBANKED | 0x08), XJ600_ERXRDPTL = (UNBANKED | 0x0A), XJ600_ERXWRPTL = (UNBANKED | 0x0C), XJ600_EUDARDPTL = (UNBANKED | 0x0E), XJ600_EUDAWRPTL = (UNBANKED | 0x10), XJ600_EUDASTL = (SFR_COMMON | 0x16), XJ600_EUDANDL = (SFR_COMMON | 0x18), XJ600_ESTATL = (SFR_COMMON | 0x1A), XJ600_EIRL = (SFR_COMMON | 0x1C), XJ600_ECON1L = (SFR_COMMON | 0x1E) }
SFR addresses for the ENCx24J600 SPI mode.
enum encX24J600_1_byte_instructions_t { b0sel_inst = 0b11000000, b1sel_inst = 0b11000010, b2sel_inst = 0b11000100, b3sel_inst = 0b11000110, setethrst_inst = 0b11001010, fcdisable_inst = 0b11100000, fcsingle_inst = 0b11100010, fcmultiple_inst = 0b11100100, fcclear_inst = 0b11100110, setpktdec_inst = 0b11001100, dmastop_inst = 0b11010010, dmacksum_inst = 0b11011000, dmacksums_inst = 0b11011010, dmacopy_inst = 0b11011100, dmacopys_inst = 0b11011110, settxrts_inst = 0b11010100, enablerx_inst = 0b11101000, disablerx_inst = 0b11101010, seteie_inst = 0b11101100, clreie_inst = 0b11101110 }
SPI single byte instructions.
enum encX24J600_2_byte_instructions_t { rbsel_inst = 0b11001000 }
SPI two byte instructions.
enum encX24J600_3_byte_instructions_t { rgprdpt_inst = 0b01100010, rrxrdpt_inst = 0b01100110, rgpwrpt_inst = 0b01101110, rrxwrpt_inst = 0b01110010, rudawrpt_inst = 0b01110110, wgprdpt_inst = 0b01100000, wrxrdpt_inst = 0b01100100, wgpwrpt_inst = 0b01101100, wrxwrpt_inst = 0b01110000, wudawrpt_inst = 0b01110100 }
SPI three byte instructions.
enum encX24J600_N_byte_instructions_t { rcr_inst = 0b00000000, wcr_inst = 0b01000000, bfs_inst = 0b10000000, bfc_inst = 0b10100000, rcru_inst = 0b00100000, wcru_inst = 0b00100010, bfsu_inst = 0b00100100, bfcu_inst = 0b00100110, rgpdata_inst = 0b00101000, rrxdata_inst = 0b00101100, rudadata_inst = 0b00110000, wgpdata_inst = 0b00101010, wrxdata_inst = 0b00101110, wudadata_inst = 0b00110010 }
SPI N byte instructions.
1.6.5.5 Variables
1.6.5.6 Detailed Description
This header file provides the serial interface API for the ENCx24J600 devices.
ENCx24J600 spi Header File
1.6.5.7 Macro Definition Documentation
1.6.5.7.1 BANK_MASK
#define BANK_MASK 0xE0
1.6.5.7.2 byteReverse24
#define byteReverse24( a) (((((uint32_t)a & (uint32_t)0x00FF00) >> 8) | (((uint32_t)a & (uint32_t)0x0000FF) << 8)) << 8 | (uint32_t)a >> 0x10)
1.6.5.7.3 byteReverse32
#define byteReverse32( a)
Value:
((((uint32_t)a & (uint32_t)0xff000000) >> 24) | \ (((uint32_t)a & (uint32_t)0x00ff0000) >> 8) | \ (((uint32_t)a & (uint32_t)0x0000ff00) << 8) | \ (((uint32_t)a & (uint32_t)0x000000ff) << 24))
1.6.5.7.4 byteSwap16
#define byteSwap16( a) ((((uint16_t)a & (uint16_t)0xFF00) >> 8) | (((uint16_t)a & (uint16_t)0x00FF) << 8))
1.6.5.7.5 convert_hton24
#define convert_hton24( a) byteReverse24(a)
1.6.5.7.6 htonl
#define htonl( a) byteReverse32(a)
1.6.5.7.7 htons
#define htons( a) byteSwap16(a)
1.6.5.7.8 ntohl
#define ntohl( a) byteReverse32(a)
1.6.5.7.9 ntohs
#define ntohs( a) byteSwap16(a)
1.6.5.7.10 SFR_BANK0
#define SFR_BANK0 0x00
1.6.5.7.11 SFR_BANK1
#define SFR_BANK1 0x20
1.6.5.7.12 SFR_BANK2
#define SFR_BANK2 0x40
1.6.5.7.13 SFR_BANK3
#define SFR_BANK3 0x60
1.6.5.7.14 SFR_COMMON
#define SFR_COMMON 0xE0
1.6.5.7.15 SFR_MASK
#define SFR_MASK 0x1F
1.6.5.7.16 UNBANKED
#define UNBANKED 0X80
1.6.5.8 Enumeration Type Documentation
1.6.5.8.1 sfr_bank_t
enum sfr_bank_t
| sfr_bank0 |
Bank 0 |
| sfr_bank1 |
Bank 1 |
| sfr_bank2 |
Bank 2 |
| sfr_bank3 |
Bank 3 |
| sfr_common |
Common Set of Registers (last five locations of each bank) |
| sfr_bank0 |
Bank 0 |
| sfr_bank1 |
Bank 1 |
| sfr_bank2 |
Bank 2 |
| sfr_bank3 |
Bank 3 |
| sfr_common |
Common Set of Registers (last five locations of each bank) |
1.6.5.9 Variable Documentation
1.6.5.9.1 rxPacketStatusVector
receiveStatusVector_t rxPacketStatusVector
1.6.5.9.2 TXPacketSize
uint16_t TXPacketSize
1.6.6 source/encx24j600_types.h File Reference
1.6.6.1 Macros
#define RAMSIZE_ETH 0x6000ul
#define TXSTART 0x0000ul
Transmit buffer start.
#define TXEND 0x15FFul
Transmit buffer end.
#define RXSTART 0x1600ul
Receive buffer start (must be an even memory address).
#define RXEND (RAMSIZE_ETH - 2)
Receive buffer end.
#define ETH_HEADER_SIZE 14
#define IP_PROTOCOL_POS 23
#define ESTAT_PHYLINK 0x0100
#define ESTAT_RSTDONE 0x0800
#define ESTAT_PHYDPX 0x0400
#define ESTAT_PHYRDY 0x0200
#define ESTAT_PKTCNT 0x00FF
#define ESTAT_RXBUSY 0x2000
#define ESTAT_CLKRDY 0x1000
#define MACON2_FULDPX_ON 0x0001
#define MACON2_FULDPX_OFF 0xFFFE
#define EIR_CRYPTEN 0x8000
#define EIR_LINKIF 0x0800
#define EIR_TXIF 0x0008
#define EIR_PKTIF 0x0040
#define EIR_RXABTIF 0x0002
#define EIR_PCFULIF 0x0001
#define ECON1_RXEN 0x0001
#define ECON1_TXRTS 0x0002
#define ECON1_DMANOCS 0x0004
#define ECON1_DMACSSD 0x0008
#define ECON1_DMACPY 0x0010
#define ECON1_DMAST 0x0020
#define ECON1_PKTDEC 0x0100
#define ECON1_AESST 0x0800
#define ECON1_HASHLST 0x1000
#define ECON1_HASHOP 0x2000
#define ECON1_HASHEN 0x4000
#define ECON1_MODEXST 0x8000
#define PHCON1_PSLEEP 0x0800
Bit mask for PHY Sleep Enable bit. Physical Layer (PHY) power is down.
#define PHCON1_PWAKE 0xF7FF
Bit mask for PHY Wake-Up as a normal operation.
#define ECON2_ETHEN 0x8000
#define ECON2_AUTOFC 0x0080
#define ECON2_STRCH 0x4000
#define ECON2_ETHRST 0x0010
#define ECON2_RXRST 0x0020
1.6.6.2 Enumerations
1.6.6.3 Detailed Description
ENCx24J600 Ethernet Controller Header File
1.6.6.4 Macro Definition Documentation
1.6.6.4.1 ECON1_AESST
#define ECON1_AESST 0x0800
1.6.6.4.2 ECON1_DMACPY
#define ECON1_DMACPY 0x0010
1.6.6.4.3 ECON1_DMACSSD
#define ECON1_DMACSSD 0x0008
1.6.6.4.4 ECON1_DMANOCS
#define ECON1_DMANOCS 0x0004
1.6.6.4.5 ECON1_DMAST
#define ECON1_DMAST 0x0020
1.6.6.4.6 ECON1_HASHEN
#define ECON1_HASHEN 0x4000
1.6.6.4.7 ECON1_HASHLST
#define ECON1_HASHLST 0x1000
1.6.6.4.8 ECON1_HASHOP
#define ECON1_HASHOP 0x2000
1.6.6.4.9 ECON1_MODEXST
#define ECON1_MODEXST 0x8000
1.6.6.4.10 ECON1_PKTDEC
#define ECON1_PKTDEC 0x0100
1.6.6.4.11 ECON1_RXEN
#define ECON1_RXEN 0x0001
1.6.6.4.12 ECON1_TXRTS
#define ECON1_TXRTS 0x0002
1.6.6.4.13 ECON2_AUTOFC
#define ECON2_AUTOFC 0x0080
1.6.6.4.14 ECON2_ETHEN
#define ECON2_ETHEN 0x8000
1.6.6.4.15 ECON2_ETHRST
#define ECON2_ETHRST 0x0010
1.6.6.4.16 ECON2_RXRST
#define ECON2_RXRST 0x0020
1.6.6.4.17 ECON2_STRCH
#define ECON2_STRCH 0x4000
1.6.6.4.18 EIR_CRYPTEN
#define EIR_CRYPTEN 0x8000
1.6.6.4.19 EIR_LINKIF
#define EIR_LINKIF 0x0800
1.6.6.4.20 EIR_PCFULIF
#define EIR_PCFULIF 0x0001
1.6.6.4.21 EIR_PKTIF
#define EIR_PKTIF 0x0040
1.6.6.4.22 EIR_RXABTIF
#define EIR_RXABTIF 0x0002
1.6.6.4.23 EIR_TXIF
#define EIR_TXIF 0x0008
1.6.6.4.24 ESTAT_CLKRDY
#define ESTAT_CLKRDY 0x1000
1.6.6.4.25 ESTAT_PHYDPX
#define ESTAT_PHYDPX 0x0400
1.6.6.4.26 ESTAT_PHYLINK
#define ESTAT_PHYLINK 0x0100
1.6.6.4.27 ESTAT_PHYRDY
#define ESTAT_PHYRDY 0x0200
1.6.6.4.28 ESTAT_PKTCNT
#define ESTAT_PKTCNT 0x00FF
1.6.6.4.29 ESTAT_RSTDONE
#define ESTAT_RSTDONE 0x0800
1.6.6.4.30 ESTAT_RXBUSY
#define ESTAT_RXBUSY 0x2000
1.6.6.4.31 ETH_HEADER_SIZE
#define ETH_HEADER_SIZE 14
1.6.6.4.32 IP_PROTOCOL_POS
#define IP_PROTOCOL_POS 23
1.6.6.4.33 MACON2_FULDPX_OFF
#define MACON2_FULDPX_OFF 0xFFFE
1.6.6.4.34 MACON2_FULDPX_ON
#define MACON2_FULDPX_ON 0x0001
1.6.6.4.35 RAMSIZE_ETH
#define RAMSIZE_ETH 0x6000ul
1.6.7 source/physical_layer_interface.h File Reference
#include <stdbool.h> #include <stdint.h>
1.6.7.1 Data structures
struct ethernetDriver_t
struct txPacket_t
union mac48Address_t
MAC Address (48-bits).
union mac64Address_t
MAC Address (64-bits).
1.6.7.2 Functions
void ETH_Init (void)
Sets up the Ethernet and starts the execution. Initializes the TX/RX buffer, the MAC and the PHY.
void ETH_EventHandler (void)
Manages the MAC events. Can be used for polling or for new events in Interrupt Service Routine (ISR).
void ETH_NextPacketUpdate (void)
Updates the pointers for the next available RX packets. Retrieves information about the last received packet and the address of the next ones.
void ETH_ResetReceiver (void)
Resets the receiver buffer.
void ETH_SendSystemReset (void)
Resets the system software.
const mac48Address_t * MAC_getAddress (void)
Returns the MAC address of type mac48Address_t.
uint16_t ETH_ReadBlock (void *buffer, uint16_t length)
Reads a block of data from the RX buffer MAC.
uint8_t ETH_Read8 (void)
Reads one byte of data from the RX buffer MAC.
uint16_t ETH_Read16 (void)
Reads two bytes of data from the RX buffer and returns them in host order.
uint32_t ETH_Read24 (void)
Reads three bytes of data from the RX buffer and returns them in host order.
uint32_t ETH_Read32 (void)
Reads four bytes of data from the RX buffer and returns them in host order.
void ETH_Dump (uint16_t length)
Drops the N bytes from a packet list when the data is lost. Clears a number of bytes (length) from the RX buffer.
void ETH_Flush (void)
Drops the rest of this packet and release the buffer. Clears all bytes from the RX buffer.
uint16_t ETH_GetFreeTxBufferSize (void)
Returns the available space size in the Ethernet TX buffer.
phy_error_msg ETH_WriteStart (const mac48Address_t *dest_mac, uint16_t type)
Starts a packet if the Ethernet transmitter is idle.
uint16_t ETH_WriteString (const char *string)
Writes a string of data into the MAC.
uint16_t ETH_WriteBlock (const char *data, uint16_t length)
Writes a block of data into the TX buffer MAC.
void ETH_Write8 (uint8_t data)
Writes one byte of data into the TX buffer MAC.
void ETH_Write16 (uint16_t data)
Writes two bytes into the TX buffer MAC in Network order.
void ETH_Write24 (uint32_t data)
Writes three bytes into the TX buffer MAC in Network order.
void ETH_Write32 (uint32_t data)
Writes four bytes into the TX buffer MAC in Network order.
void ETH_Insert (char *data, uint16_t len, uint16_t offset)
Inserts N data bytes into a specific offset in the TX buffer/packet.
phy_error_msg ETH_Copy (uint16_t len)
Copies N bytes from the saved read location (RX buffer) into the current TX location (TX buffer) using the DMA set up. This is used for ICMP ECHO to eliminate the need to extract the arbitrary payload.
phy_error_msg ETH_Send (void)
Sends the TX packet. Starts the transmission of packet or queues the packet that has been created.
uint16_t ETH_TxComputeChecksum (uint16_t position, uint16_t length, uint16_t seed)
Calculates the hardware checksum of length bytes starting with the position.
uint16_t ETH_RxComputeChecksum (uint16_t len, uint16_t seed)
Calculates the RX software checksum.
void ETH_GetMAC (uint8_t *macAddr)
Reads the MAC address.
void ETH_SetMAC (uint8_t *macAddr)
Sets the MAC address.
uint16_t ETH_GetWritePtr (void)
Returns the value of the write pointer.
void ETH_SaveRDPT (void)
Saves the receive pointer for copy.
void ETH_ResetReadPtr (void)
Resets the receive pointer to the Init.
uint16_t ETH_GetReadPtr (void)
Returns the value of the read pointer.
void ETH_SetReadPtr (uint16_t rdptr)
Sets the read pointer to a specific address.
uint16_t ETH_GetStatusVectorByteCount (void)
Returns the Status Vector's byte count.
void ETH_SetStatusVectorByteCount (uint16_t bc)
Sets the Status Vector's byte count.
void ETH_ResetByteCount (void)
Resets the driver's byte count.
uint16_t ETH_GetByteCount (void)
Returns the the driver's byte count.
uint16_t ETH_ReadSavedWRPT (void)
Returns the saved write pointer.
void ETH_SaveWRPT (void)
Saves the write pointer for copy.
void ETH_SetRxByteCount (uint16_t count)
Sets the receiver's byte count.
uint16_t ETH_GetRxByteCount (void)
Returns the receiver's byte count.
bool ETH_CheckLinkUp (void)
Checks for the link.
void ETH_TxReset (void)
Resets the transmitter.
void ETH_MoveBackReadPtr (uint16_t offset)
Moves back the read pointer.
1.6.7.3 Macros
#define ETH_packetReady() ethData.pktReady
#define ETH_linkCheck() ethData.up
#define ETH_linkChanged() ethData.linkChange
1.6.7.4 Enumerations
enum phy_error_msg { PHY_ERROR = 0, PHY_SUCCESS, PHY_LINK_NOT_FOUND, PHY_BUFFER_BUSY, PHY_TX_LOGIC_NOT_IDLE, PHY_TX_QUEUED, PHY_DMA_TIMEOUT }
PHY status/errors.
1.6.7.5 Variables
volatile ethernetDriver_t ethData
const mac48Address_t broadcastMAC
1.6.7.6 Detailed Description
Physical Layer Interface Header File
1.6.7.7 Macro Definition Documentation
1.6.7.7.1 ETH_linkChanged
#define ETH_linkChanged( ) ethData.linkChange
1.6.7.7.2 ETH_linkCheck
#define ETH_linkCheck( ) ethData.up
1.6.7.7.3 ETH_packetReady
#define ETH_packetReady( ) ethData.pktReady
1.6.7.8 Variable Documentation
1.6.7.8.1 broadcastMAC
const mac48Address_t broadcastMAC
1.6.7.8.2 ethData
volatile ethernetDriver_t ethData
1.6.7.8.3 hostMacAddress
mac48Address_t hostMacAddress