20.5.5 Control Register E Clear - Normal Mode
Use this register instead of a Read-Modify-Write (RMW) to clear individual bits by
writing a ‘1
’ to its bit location.
Name: | CTRLECLR |
Offset: | 0x04 |
Reset: | 0x00 |
Property: | - |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CMD[1:0] | LUPD | DIR | |||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bits 3:2 – CMD[1:0] Command
This bit field is used for software control of update, restart, and Reset of the
timer/counter. The command bit field is always read as ‘0
’.
Value | Name | Description |
---|---|---|
0x0 | NONE | No command |
0x1 | UPDATE | Force update |
0x2 | RESTART | Force restart |
0x3 | RESET | Force hard Reset (ignored if the timer/counter is enabled) |
Bit 1 – LUPD Lock Update
Lock update can be used to ensure that all buffers are valid before an update is performed. This setting will not prevent an update issued by the Command bit field.
Value | Description |
---|---|
0 | The buffered registers are updated as soon as an UPDATE condition has occurred |
1 | No update of the buffered registers is performed, even though an UPDATE condition has occurred |
Bit 0 – DIR Counter Direction
Normally this bit is controlled in hardware by the Waveform Generation mode or by event actions, but can also be changed from the software.
Value | Description |
---|---|
0 | The counter is counting up (incrementing) |
1 | The counter is counting down (decrementing) |