| Document |
The content for the devices described in this document has been
restructured from:
- ATtiny212/412
Data Sheet
- ATtiny214/414/814
Data Sheet
- ATtiny416/816
Data Sheet
- ATtiny417/817
Data Sheet
to:
- ATtiny212/214/412/414/416 Data Sheet (this
document)
- ATtiny417/814/816/817 Data Sheet
Refer to 40.2 Appendix - Obsolete Revision
History for further details.The following items are
referring to changes between the latest revisions of the obsolete
documents and this document:
- Updated the
document to Microchip editing standard
- Updated terminology used throughout data sheet:
- Master is replaced by host
- Slave is replaced by client
- Removed related
links
- Removed the
Acronyms and Abbreviations section
- Removed the
content of the Instruction Set Summary section. This
section now refers to the external Instruction Set Manual
instead.
- Removed
device-specific information from peripheral sections
- Restructured
sections related to system dependencies within the peripheral
sections
|
| Device |
- Device-specific
information is restructured/changed to comply with the devices
documented in this document
- Features
- Pinout
- I/O
Multiplexing and Considerations
- Ordering
Information
- Package
Drawings
- Block diagram updated
- Pinout diagrams
updated:
- 8-Pin SOIC
- 14-Pin SOIC
- 20-Pin
SOIC
- 20-Pin
VQFN
- Memories
- Flash and the Three Sections figure
added(3)
- Memory
Map figure updated
- Memory
Section Access from CPU and UPDI on Locked
Device section added
- Fuse
Description section updated with
factory-programmed default values
- Peripherals and
Architecture
- Peripheral Address Match table updated
- Interrupt Vector Mapping table updated
- Base Address column renamed to Program
Address (word)
- Peripheral Source column cleaned up
- Definition column renamed to
Description and cleaned up
- Package
Drawings
- Drawing Numbers table updated
- Tables
removed as the information is available on the Microchip
website:
- Device Package and Maximum Weight
- Package Characteristics
- Package Reference
- Thermal Considerations section updated and
moved inside the Package Drawings section
|
| AVR CPU |
- Updated Features section
- Removed duplicate
information after the AVR CPU architecture
- Emphasized that
the Arithmetic Logic Unit (ALU) is doing its operations against
working registers in the register file
- Added Stack
Pointer Instructions table
- Restructured and
improved documentation in the following sections:
- Register File
- X-,
Y-, and Z-Registers
- Accessing 16-bit Registers
- Added Accessing 24-Bit Registers section
- Added On-Chip
Debug Capabilities section
- Updated bit names
in the Status Register (SREG):
- From
Bit Copy Storage to Transfer Bit
- From
Sign Bit to Sign Flag
|
| NVMCTRL |
- Updated
NVMCTRL Block Diagram figure
- Write
Access After Reset section added
|
| CLKCTRL |
- Updated CLKCTRL Block Diagram figure(1,2)
- Updated Signal Description section(1,2)
- Updated Main Clock and Prescaler
figure(1)
- Updated External Clock Sources section(1)
- Added 32.768 kHz Crystal Oscillator (XOSC32K)
section(1)
- Updated CLKSEL bit field in MCLKCTRLA
register(1)
- Added XOSC32KS bit in MCLKSTATUS(1)
- Added XOSC32KCTRLA register(1)
|
| SLPCTRL |
- Updated Sleep
Mode Activity Overview tables
|
| RSTCTRL |
- Updated Block Diagram figure
- Figures added:
- MCU
Start-up, RESET Tied to
VDD
- Brown-out Detector Reset
- External Reset Characteristics
- Watchdog Reset
- Software Reset
- Added Domains Affected By Reset section
|
| CPUINT |
- Added Minimum
Interrupt Response Time table
- General
improvement of the documentation and its structure
|
| EVSYS |
- Register names
updated
- From
ASYNCCH to ASYNCCHn
- From
SYNCCH to SYNCCHn
- From
ASYNCUSER to ASYNCUSERn
- From
SYNCUSER to SYNCUSERn
- Bit field descriptions updated
- ASYNCCHn.ASYNCCH
- SYNCCHn.SYNCCH
|
| PORT |
- Updated Block
Diagram figure
- Added
Asynchronous Sensing Pin Properties added
- Added Event
Generators in PORTx table
- General
improvement of the documentation and its structure
|
| BOD |
- Block diagram
updated
- Offset in the
Available Interrupt Vectors and Sources table
removed
- Name column added
to bit field description tables:
- CTRLA.ACTIVE
- CTRLA.SLEEP
- INTCTRL.VLMCFG
|
| WDT |
- Updated values in
the CTRLA.PERIOD bit field description
|
| TCA |
- Updated Block
Diagram figure
- Updated
Timer/Counter Clock Logic figure
- Updated Signal
Description table
- Update Single-Slope Pulse-Width Modulation figure
- Updated
Timer/Counter Block Diagram Split Mode figure
- Added Event
Generators in TCA table
- Added Event
Users in TCA table
- Removed offset in
the Available Interrupt Vectors and Sources in Normal
Mode and Available Interrupt Vectors and Sources in
Split mode tables
- Combined tables
for the CTRLB.WGMODE bit field into one
- Added bit fields:
- CTRLECLR.CMDEN
- CTRLESET.CMDEN
- General
improvement of the documentation and its structure
|
| TCB |
- Updated Block
Diagram figure
- Timer/Counter
Clock Logic figure added
- Figures
updated:
- Periodic Interrupt Mode
- Time-Out Check Mode
- Input
Capture on Event
- Input
Capture Frequency Measurement
- Input
Capture Pulse-Width Measurement
- Input
Capture Frequency and Pulse-Width
Measurement
- Single-Shot Mode
- 8-Bit
PWM Mode
- Added Event
Generators in TCB table
- Added Event
Users and Available Event Actions in TCB table
- Removed offset in
the Available Interrupt Vectors and Sources table
- Name column added
to bit field description tables:
- CTRLA.CLKSEL
- CTRLB.CNTMODE
|
| TCD |
- Updated Block
Diagram figure
- Added Event
Generators in TCD table
- Added Event Users and Available Event Actions in TCD
table
- Removed offset in
the Available Interrupt Vectors and Sources table
- Added name column
to bit field description tables:
- CTRLA.CLKSEL
- CTRLA.CNTPRES
- CTRLA.SYNCPRES
- CTRLA.ENABLE
- DLYCTRL.DLYPRESC
- DLYCTRL.DLYSEL
- General
improvement of the documentation and its structure
|
| RTC |
- Updated Block Diagram figure
- Event
Generators in RTC table added
- Removed offset in
the Available Interrupt Vectors and Sources table
- Added name column
to the bit field description table for CLKSEL.CLKSEL
- General
improvement of the documentation and its structure
|
| USART |
- Added information about TXD buffer in:
- Block Diagram figure
- Overview section
- Data
Transmission section
- Event
Generators in USART table added
- Event Users in
USART table added
- Offset in the
Available Interrupt Vectors and Sources table
removed
- General
improvement of the documentation and its structure
- Updated terminology:
- Master is replaced by host
- Slave is replaced by client
|
| SPI |
- Updated Block
Diagram figure
- Added Event
Generators in SPI table
- Removed offset in
the Available Interrupt Vectors and Sources table
- Interrupt
Flags register separate for Normal and Buffer mode
- General
improvement of the documentation and its structure
- Updated terminology:
- Master is replaced by host
- Slave is replaced by client
|
| TWI |
- Offset in the
Available Interrupt Vectors and Sources table
removed
- Name column added
to bit field description tables:
- CTRLA.FMPEN
- MCTRLB.ACKACT
- MCTRLB.MCMD
- General
improvement of the documentation and its structure
- Updated terminology:
- Master is replaced by host
- Slave is replaced by client
|
| CRCSCAN |
- Updated Block Diagram figure(1)
- Offset in the
Available Interrupt Vectors and Sources table
removed
|
| CCL |
- Updated Block Diagram figure
- Replaced Lookup Table Logic section with Truth Table
Logic section
- Updated Clock Source Settings figure
- Updated bit field
description of TRUTHn.TRUTHn
|
| AC |
- DACREF removed as
an internal input
|
| ADC |
- Updated
Block Diagram figure
- Moved Definitions to ADC Parameter Definitions
in Conventions section
- Removed PTC Operation section(2,3)
- Removed
offset in the Available Interrupt Vectors and Sources
table
- Updated the
CTRLA.MUXPOS bit field description
|
| DAC |
|
| PTC |
- PTC section removed (2,3)
|
| UPDI |
- Updated
figures:
- UPDI
Clock Domains
- UPDI
Instruction Set Overview
- LDS
Instruction Operation
- STS
Instruction Operation
- LD
Instruction Operation
- ST
Instruction Operation
- LCDS
Instruction Operation
- STCS
Instruction Operation
- REPEAT
Instruction Operation
- Inter
Delay Example with LD and RPT
- Added
sections:
- BREAK
in One-Wire mode
- SYNCH and SYNCH in One-Wire mode
- Extended and
improved the documentation related to enabling the UPDI
peripheral
- Extended and
improved the documentation related to disabling the UPDI
peripheral
- Renamed the
UPDI Enable with 12V Override of RESET pin section to
UPDI Enable with High-Voltage Override of RESET
pin
- Added the
REPEAT Used With LD Instruction Operation figure
- Added Event
Generators in UPDI table
- Removed
implementation-specific details that are considered as not
useful for the end users
|
| Electrical Characterization |
- Added Maximum Frequency vs. VDD for [-40, 125]°C,
Extended Temperature Range figure
- Added maximum
numbers to the Power Consumption section
- Rounded numbers
in the Peripherals Power Consumption table
- Added TCD
section
- Updated TWI -
Timing Requirements figure
- Updated numbers
for tOF in the TWI - Timing Characteristics
table
- Added typical values for tHD;STA,
tSU;STA, tSU;STO and tBUF
- Added SDA Hold
Time table
- Added TEMPSENSE
section
- Updated
Accuracy Characteristics table for DAC
- Updated tables in
the AC section
- Removed
PTC section(2,3)
- Added UPDI
Max. Bit Rates vs. VDD table
- Replaced Chip
Erase with Chip Erase with UPDI in the
Programming Times table
|
| Typical Characterization |
- Updated Power Consumption plots
- Added
Temperature Sensor Error vs. Temperature ±3σ
figure
- Added TWI SDA
Hold Time vs. Temperature figure
- Removed PTC Characteristics section(2,3)
|
