25.3.2.1.3 SS Pin Functionality in Host Mode - Multi-Host Support

In Host mode, the Client Select Disable (SSD) bit in the Control B (SPIn.CTRLB) register controls how the SPI uses the SS pin.

  • If SSD in SPIn.CTRLB is ‘0’, the SPI can use the SS pin to transition from Host to Client mode. This allows multiple SPI hosts on the same SPI bus.

  • If SSD in SPIn.CTRLB is ‘0’, and the SS pin is configured as an output pin, it can be used as a regular I/O pin or by other peripheral modules and will not affect the SPI system

  • If SSD in SPIn.CTRLB is ‘1’, the SPI does not use the SS pin. It can be used as a regular I/O pin or by other peripheral modules.

If the SSD bit in SPIn.CTRLB is ‘0’, and the SS is configured as an input pin, the SS pin must be held high to ensure Host SPI operation. A low level will be interpreted as another Host is trying to take control of the bus. This will switch the SPI into Client mode, and the hardware of the SPI will perform the following actions:
  1. The Host (MASTER) bit in the SPI Control A (SPIn.CTRLA) register is cleared, and the SPI system becomes a client. The direction of the SPI pins will be switched when the conditions in Table 25-2 are met.
  2. The Interrupt Flag (IF) bit in the Interrupt Flags (SPIn.INTFLAGS) register will be set. If the interrupt is enabled and the global interrupts are enabled, the interrupt routine will be executed.
Table 25-2. Overview of the SS Pin Functionality when the SSD Bit in SPIn.CTRLB is ‘0’
SS Configuration SS Pin-Level Description
Input High Host activated (selected)
Low Host deactivated, switched to Client mode
Output High Host activated (selected)
Low
Note: If the device is in Host mode and it cannot be ensured that the SS pin will stay high between two transmissions, the status of the Host (MASTER) bit in SPIn.CTRLA has to be checked before a new byte is written. After the Host bit has been cleared by a low level on the SS line, it must be set by the application to re-enable the SPI Host mode.