1.2.1 ADC Offset Error Specification Lowered in ECH, ECM and ECL Modes
When operating the device using an external clock source as the system clock in ECH, ECM or ECL mode, the ADC Offset Error (AD04: EOFF) is updated to 12 Least Significant bits.
Work around
To meet the specified ADC Offset Error limit of 6 Least Significant bits, do not operate the device using the system clock in ECH, ECM or ECL mode when using the ADC.
Affected Silicon Revisions
| D1 | D3 | E0 |
| X |