Introduction

The PIC18F04/05/14/15Q40 devices you have received conform functionally to the current device data sheet (DS40002236E), except for the anomalies described in this document.

The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in the table below.

The errata described in this document will be addressed in future revisions of the PIC18F04/05/14/15Q40 silicon.

Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current.

Table . Silicon Device Identification
Part Number	Device ID	Revision ID
Part Number	Device ID	D1	D3	E0
PIC18F04Q40	0x7640	0xA0C1	0xA0C3	0xA0D0
PIC18F05Q40	0x7600	0xA0C1	0xA0C3	0xA0D0
PIC18F14Q40	0x7620	0xA0C1	0xA0C3	0xA0D0
PIC18F15Q40	0x75E0	0xA0C1	0xA0C3	0xA0D0

Important: Refer to the Device/Revision ID section in the current “PIC18FXXQ40 Family Programming Specification” (DS40002185) for more detailed information on Device Identification and Revision IDs for your specific device.

Table . Silicon Issue Summary
Module	Feature	Item No.	Issue Summary	Affected Revisions
Module	Feature	Item No.	Issue Summary	D1	D3	E0
Analog-to-Digital Converter with Computation	ADCC	Double Sample Conversions	Double Sample Conversions	X	X
Electrical Specifications	ADC Offset Error	ADC Offset Error Specification Lowered in ECH, ECM and ECL Modes	ADC Offset Error specification lowered in ECH, ECM and ECL modes	X
I²C	I²C	The I²C Start and/or Stop Flags May Be Set When I²C Is Enabled	I²C Start and/or Stop flags may be set When I²C is enabled	X
		MDR Bit Is Not Cleared after Bus Time-Out	MDR bit is not cleared after Bus Timeout	X	X	X
		Bus Time-Out Not Detected Properly When External Host Clock Stretches	Bus Timeout not detected properly when External Host Clock stretches	X	X	X
		Clock Stretch Disable Not Working Properly	Clock Stretch Disable not working properly	X	X	X
		Bus Time-Out Causes False Start/Stop	Bus Timeout causes false Start/Stop	X	X	X
Universal Asynchronous Receiver Transmitter	UART	UART TXDE Signal May Go Low Before the STOP Bit Has Been Entirely Transmitted	UART TXDE signal may go low before the STOP bit has been entirely transmitted	X	X	X
Universal Asynchronous Receiver Transmitter	UART	Asynchronous 9-bit UART Address Mode Address Mismatch	Asynchronous 9-bit UART Address mode address mismatch	X	X
Signal Measurement TImer	SMT	Reset Bit	Reset Bit	X	X
PIC18 CPU	FSR Shadow Registers	FSR Shadow Registers Are Not Writable	FSR Shadow Registers are not writable	X	X
ICSP™	Low-Voltage Programming (LVP)	Low-Voltage Programming Not Possible	Low Voltage Programming is not possible when VDD is below BORV while BOR is enabled	X	X	X
Instruction Set	`PUSHL` Instruction	1.8.1	The `PUSHL` instruction incorrectly executes	X	X	X
Note: Only those issues indicated in the last column apply to the current silicon revision.