CCL BLDC Fan Controller Implementation

Some basic elements and features that are often needed for operating a BLDC motor with a microcontroller are PWM control signals, a Hall sensor input signal, motor commutation, and PWM dead-time insertion. For a simple BLDC fan motor with two drive signal inputs and a Hall sensor output, the resulting waveforms when the motor is rotating looks similar as illustrated in the figure below. The names of the waveforms in the figure are the names of the specific module signals selected for design and implementation of the application described in this document.

By making the device produce the outlined waveforms based on the provided Hall sensor signal, it will act as a simple BLDC Fan Controller. As the name of the application note suggests, the Configurable Custom Logic (CCL) plays the main role in accomplishing this.
Figure 1. Sketch of Relevant Waveforms for the CCL BLDC Fan Controller

The Configurable Custom Logic (CCL) module

The Configurable Custom Logic (CCL) module is a programmable logic peripheral, which can be connected to the device pins, events, or peripherals. This allows the user to eliminate external logic gates for simple glue logic functions on the PCB, reducing bill-of-materials (BOM) cost. Each LUT consists of three inputs, a truth table, and a filter/edge detector. Each LUT can generate an output as a user programmable logic expression with three inputs.

Implementation Overview

From examining the waveforms in the figure above, it can be seen that the logical value of the signals PWM A and PWM B are each given by a combination of the logical values of the three other signals. This represents a typical use case for the CCL module, which can generate the two desired signals by using the Hall sensor signal, base PWM signal, and dead-time signal as inputs.

The Hall sensor signal waveform can be generated by connecting the physical Hall sensor to the Analog Comparator (AC) module, while the 16-bit Timer/Counter Type A (TCA) is suited for generating the base PWM signal, also called "pulse train". By combining two additional device modules, it is also possible to create the dead-time signal. The signal from the Analog Comparator (AC) can be routed through the Event System (EVSYS) to 16-bit Timer/Counter Type B (TCB). In 16-bit Timer/Counter Type B (TCB) it can be used to trigger a square wave which will represent the dead-time signal in the Configurable Custom Logic (CCL) module.

An overview of the involved modules is presented in the figure below. By configuring these correctly, a controller for a simple BLDC fan that performs motor commutation and dead-time insertion without using the CPU can be realized. A more specific description of how the different modules are set up is presented in the following sections.

Figure 2. Overview of Utilized Device Modules and Signals

Configurable Custom Logic (CCL) Setup

Two programmable Look-up Tables, also referred to as LUTs or Truth tables, are needed to output two separate PWM signals. Enabling of the LUTs and sending the outputs to pads is done by writing to the CTRLA register of each LUT. Since the value of both output signals is given by a combination of the Hall sensor signal, the dead-time signal, and the base PWM signal, both LUTs are set up to take these three inputs by writing to their respective CTRLB and CTRLC registers.

The behavior of each LUT is determined by its truth table, which is set up by writing to its respective TRUTH register. The hexadecimal value to be written to the TRUTH registers for this application is determined from TRUTHn[0:7] to be 0x02 for LUT0 and 0x08 for LUT1, as shown in the table below. The two figures following the table illustrate the two LUT setups using logic gates. Which signal is routed to what LUT input can be seen from the table and the figures below.

Table 1. Truth Table for LUT0 and LUT1 with Identical Input Selection
0 0 0 0 (TRUTH0[0]) 0 (TRUTH1[0])
0 0 1 1 (TRUTH0[1]) 0 (TRUTH1[1])
0 1 0 0 (TRUTH0[2]) 0 (TRUTH1[2])
0 1 1 0 (TRUTH0[3]) 1 (TRUTH1[3])
1 0 0 0 (TRUTH0[4]) 0 (TRUTH1[4])
1 0 1 0 (TRUTH0[5]) 0 (TRUTH1[5])
1 1 0 0 (TRUTH0[6]) 0 (TRUTH1[6])
1 1 1 0 (TRUTH0[7]) 0 (TRUTH1[7])

Figure 3. LUT0 Logic
Figure 4. LUT1 logic

The values of the two TRUTH registers implement the desired behavior for the LUTs according to the illustrated waveform in the introduction of this chapter. The output of LUT0 will follow the base PWM signal as long as the dead-time signal is low and the Hall sensor signal is low, while the LUT1 output will follow the base PWM signal as long as the dead-time signal is low and the Hall sensor signal is high.

Analog Comparator (AC), Voltage Reference (VREF), and Digital-to-Analog Converter (DAC) Setup

To provide the status of the connected Hall sensor, which indicates the position of the fan rotor, the Analog Comparator (AC) is set up to take the physical Hall sensor signal on its positive input pin and the Digital-to-Analog Converter (DAC) output as its negative input. This is set up via the MUXCTRLA register of the Analog Comparator (AC) module.

The output of the Digital-to-Analog Converter (DAC) is set to a fixed level by setting an initial input value and selecting the voltage reference. This is done by writing to the DATA register of the module, and the CTRLA register of the Voltage Reference (VREF) module, respectively.

The Analog Comparator (AC) output signal, ACOUT, will be high when the physical sensor signal is above the Digital-to-Analog Converter (DAC) output and low when it is below. This aligns with the illustrated waveform in the introduction of this chapter.

Note: The Voltage Reference (VREF) and Digital-to-Analog Converter (DAC) modules need to be set up such that the Digital-to-Analog Converter (DAC) output lies between the upper and lower steady state voltage output levels of the physical Hall sensor.

16-bit Timer/Counter Type B (TCB) and Event System (EVSYS) Setup

Inserting PWM dead time using the CCL as outlined in this application note requires a signal indicating when the PWM outputs should be held inactive during the specified dead-time period. Since the dead time should be inserted when the PWM output is to be switched from one driver signal to the other, which is indicated by the Hall sensor signal toggling its level, the insertion should be triggered by the edges of the ACOUT signal as these will coincide with the edges of the Hall sensor output.

The 16-bit Timer/Counter Type B (TCB) module has a "Single-Shot" mode that starts a single counting session upon detecting an edge on its Event input signal. It will then count until it reaches its TOP value and stops. The timer output signal TCB W0 will be high during counting and low otherwise, making it very suitable as a dead-time signal by using the ACOUT signal as Event input.

The ACOUT signal is routed to the 16-bit Timer/Counter Type B (TCB) via the Event System (EVSYS) by selecting ACOUT as input to an event channel and assigning the 16-bit Timer/Counter Type B (TCB) to be a user of the same event channel. In this application, this is set up by writing to the ASYNCCH0 and ASYNCUSER0 registers of the Event System (EVSYS), respectively. Furthermore, the 16-bit Timer/Counter Type B (TCB) is configured to Asynchronous Single-Shot mode with dual event edge detection by writing to the CTRLB and EVCTRL registers of the timer. The dead-time duration is set up through the CCMP register.

16-bit Timer/Counter Type A (TCA) Setup

The base PWM signal represents the PWM signal that will be output to either PWM A or PWM B depending on the Hall sensor signal input. 16-bit Timer/Counter Type A (TCA) is used for this purpose in this application, implicating that the period and duty cycle of the PWM outputs must be set up in this module.

The timer is configured to use basic Single-Slope PWM Generation mode by writing to its CTRLB register, while the PWM period and duty cycle is set up by writing the desired values to the PER and CMP0 registers, respectively. The TCA W0 is used directly as an input to the Configurable Custom Logic (CCL) module. Open-loop speed control of the connected BLDC motor can then be accomplished by adjusting the duty cycle between 0 and 100% of the timer period.

I/O Pin Controller (PORT) and Port Multiplexer (PORTMUX) Setup

Inputs and outputs are directed to and from the external pins of the device by setting up the I/O Pin Controller (PORT) module. Several signals in the device can be connected to an alternate pin instead of its default pin. This is configured in the Port Multiplexer (PORTMUX) module. The pins that need to be set up for this application are the positive input pin for the Analog Comparator (AC), which should be connected to the Hall sensor, and the two output pins from the Configurable Custom Logic (CCL), which should be connected to the two control inputs.