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PIC18F26/46/56Q35 Full-Featured 28/40/48-Pin Microcontrollers
Introduction
PIC18-Q35 Family Summary
Features
Operating Characteristics
Memory
Power-Saving Functionality
Digital Peripherals
Analog Peripherals
Clocking Structure
Programming/Debug Features
Block Diagram
1 Packages
2 Pin Diagrams
2.1 ***
2.2 ***
2.3 ***
2.4 ***
2.5 ***
2.6 ***
3 Pin Allocation Tables
4 Guidelines for Getting Started with PIC18-Q35 Microcontrollers
4.1 Basic Connection Requirements
4.2 Power Supply Pins
4.3 Master Clear (MCLR) Pin
4.4 In-Circuit Serial Programming™ (ICSP™) Pins
4.5 External Oscillator Pins
4.6 Unused I/Os
5 Register and Bit Naming Conventions
5.1 Register Names
5.2 Bit Names
5.3 Register and Bit Naming Exceptions
6 Register Legend
7 PIC18 CPU
7.1 System Arbitration
7.2 Memory Access Scheme
7.3 8x8 Hardware Multiplier
7.4 PIC18 Instruction Cycle
7.5 STATUS Register
7.6 Call Shadow Register
7.7 Register Definitions: System Arbiter
7.8 Register Summary - System Arbiter Control
8 Device Configuration
8.1 Configuration Settings
8.2 Enhanced Code Protection
8.3 User ID
8.4 Device ID and Revision ID
8.5 Register Definitions: Configuration Settings
8.6 Register Summary - Configuration Settings
8.7 Register Definitions: Device ID and Revision ID
8.8 Register Summary - DEVID/REVID
8.9 Register Definitions: Software ICSP Enable
9 Memory Organization
9.1 Program Memory Organization
9.2 Device Information Area
9.3 Device Configuration Information
9.4 Data Memory Organization
9.5 Data Addressing Modes
9.6 Data Memory and the Extended Instruction Set
9.7 Register Definitions: Memory Organization
9.8 Register Summary - Memory Organization
10 NVM - Nonvolatile Memory Module
10.1 Operations
10.2 Unlock Sequence
10.3 Program Flash Memory (PFM)
10.4 Data Flash Memory (DFM)
10.5 Register Definitions: NVM
10.6 Register Summary - NVM
11 VIC - Vectored Interrupt Controller Module
11.1 Overview
11.2 Interrupt Control and Status Registers
11.3 Interrupt Vector Table
11.4 Interrupt Priority
11.5 Interrupt Operation
11.6 Context Saving
11.7 Returning from Interrupt Service Routine (ISR)
11.8 Interrupt Latency
11.9 Interrupt Setup Procedure
11.10 External Interrupt Pins
11.11 Wake-Up from Sleep
11.12 Interrupt Compatibility
11.13 Register Definitions: Interrupt Control
11.14 Register Summary - Interrupts
12 OSC - Oscillator Module (With Fail-Safe Clock Monitor)
12.1 Clock Source Types
12.2 Clock Switching
12.3 Fail-Safe Clock Monitor (FSCM)
12.4 Active Clock Tuning (ACT)
12.5 Register Definitions: Oscillator Module
12.6 Register Summary - Oscillator Module
13 CRC - Cyclic Redundancy Check Module with Memory Scanner
13.1 Module Overview
13.2 Polynomial Implementation
13.3 Data Sources
13.4 CRC Check Value
13.5 CRC Interrupt
13.6 Configuring the CRC Module
13.7 Scanner Module Overview
13.8 Scanning Modes
13.9 Configuring the Scanner
13.10 Scanner Interrupts
13.11 WWDT Interaction
13.12 Operation During Sleep
13.13 Peripheral Module Disable
13.14 Register Definitions: CRC and Scanner Control
13.15 Register Summary - CRC
14 Resets
14.1 Power-on Reset (POR)
14.2 Brown-out Reset (BOR)
14.3 Low-Power Brown-out Reset (LPBOR)
14.4 MCLR Reset
14.5 Windowed Watchdog Timer (WWDT) Reset
14.6 RESET Instruction
14.7 Stack Overflow/Underflow Reset
14.8 Programming Mode Exit
14.9 Power-up Timer (PWRT)
14.10 Start-Up Sequence
14.11 Determining the Cause of a Reset
14.12 Power Control (PCON0/PCON1) Registers
14.13 Register Definitions: Power Control
14.14 Register Summary - BOR Control and Power Control
15 WWDT - Windowed Watchdog Timer
15.1 Independent Clock Source
15.2 WWDT Operating Modes
15.3 Time-Out Period
15.4 Watchdog Window
15.5 Clearing the Watchdog Timer
15.6 Operation During Sleep
15.7 Register Definitions: Windowed Watchdog Timer Control
15.8 Register Summary - WDT Control
16 DMA - Direct Memory Access
16.1 DMA Registers
16.2 DMA Organization
16.3 DMA Interface
16.4 Disable DMA Message Transfer Upon Completion
16.5 Types of Hardware Triggers
16.6 Types of Data Transfers
16.7 DMA Interrupts
16.8 DMA Setup and Operation
16.9 Reset
16.10 Power-Saving Mode Operation
16.11 Example Setup Code
16.12 Register Overlay
16.13 Register Definitions: DMA
16.14 Register Summary - DMA
17 Power-Saving Modes
17.1 Doze Mode
17.2 Sleep Mode
17.3 Idle Mode
17.4 Peripheral Operation in Power-Saving Modes
17.5 Register Definitions: Power-Savings Control
17.6 Register Summary - Power-Savings Control
18 PMD - Peripheral Module Disable
18.1 Overview
18.2 Disabling a Module
18.3 Enabling a Module
18.4 Register Definitions: Peripheral Module Disable
18.5 Register Summary - PMD
19 I/O Ports
19.1 Overview
19.2 PORTx - Data Register
19.3 LATx - Output Latch
19.4 TRISx - Direction Control
19.5 ANSELx - Analog Control
19.6 WPUx - Weak Pull-Up Control
19.7 INLVLx - Input Threshold Control
19.8 SLRCONx - Slew Rate Control
19.9 ODCONx - Open-Drain Control
19.10 Edge Selectable Interrupt-on-Change
19.11 I2C Pad Control
19.12 I/O Priorities
19.13 MCLR/VPP/RE3 Pin
19.14 Register Definitions: Port Control
19.15 Register Summary - I/O Ports
20 SRPORT – Signal Routing Port
20.1 Operation
20.2 Software Setup
20.3 Register Definitions: Signal Routing Port
20.4 Register Summary - Signal Routing Port
21 IOC - Interrupt-on-Change
21.1 Overview
21.2 Enabling the Module
21.3 Individual Pin Configuration
21.4 Interrupt Flags
21.5 Operation in Sleep
21.6 Register Definitions: Interrupt-on-Change Control
21.7 Register Summary - Interrupt-on-Change Control
22 PPS - Peripheral Pin Select Module
22.1 Overview
22.2 PPS Inputs
22.3 PPS Outputs
22.4 TRISxyPPS Register
22.5 Bidirectional Pins
22.6 PPS Lock
22.7 Operation During Sleep
22.8 Effects of a Reset
22.9 Register Definitions: Peripheral Pin Select (PPS)
22.10 Register Summary - Peripheral Pin Select Module
23 MVIO - Multi-Voltage I/O
23.1 Features
23.2 Module Overview
23.3 Operation
23.4 Register Definitions: MVIO
23.5 Register Summary - MVIO
24 CLC - Configurable Logic Cell
24.1 CLC Setup
24.2 CLC Interrupts
24.3 Effects of a Reset
24.4 Output Mirror Copies
24.5 Operation During Sleep
24.6 CLC Setup Steps
24.7 Register Overlay
24.8 Register Definitions: Configurable Logic Cell
24.9 Register Summary - CLC Control
25 CLB - Configurable Logic Block
25.1 CLB Module Enable
25.2 Basic Logic Element (BLE)
25.3 CLB Module Inputs
25.4 CLB Module Outputs
25.5 CLB Clock Selection
25.6 CLB Interrupts
25.7 Operation During Sleep Mode
25.8 CLB Configuration
25.9 CLB Debug
25.10 Register Definitions: Configurable Logic Block
25.11 Register Summary - CLB Control
26 CLKREF - Reference Clock Output Module
26.1 Clock Source
26.2 Programmable Clock Divider
26.3 Selectable Duty Cycle
26.4 Operation in Sleep Mode
26.5 Register Definitions: Reference Clock
26.6 Register Summary - Reference CLK
27 TMR0 - Timer0 Module
27.1 Timer0 Operation
27.2 Clock Selection
27.3 Timer0 Output and Interrupt
27.4 Operation During Sleep
27.5 Register Definitions: Timer0 Control
27.6 Register Summary - Timer0
28 TMR1 - Timer1 Module with Gate Control
28.1 Timer1 Operation
28.2 Clock Source Selection
28.3 Timer1 Prescaler
28.4 Secondary Oscillator
28.5 Timer1 Operation in Asynchronous Counter Mode
28.6 Timer1 16-Bit Read/Write Mode
28.7 Timer1 Gate
28.8 Timer1 Interrupt
28.9 Timer1 Operation During Sleep
28.10 CCP Capture/Compare Time Base
28.11 CCP Special Event Trigger
28.12 Peripheral Module Disable
28.13 Register Definitions: Timer1 Control
28.14 Register Summary - Timer1
29 TMR2 - Timer2 Module
29.1 Timer2 Operation
29.2 Timer2 Output
29.3 External Reset Sources
29.4 Timer2 Interrupt
29.5 PSYNC Bit
29.6 CSYNC Bit
29.7 Operating Modes
29.8 Operation Examples
29.9 Timer2 Operation During Sleep
29.10 Register Definitions: Timer2 Control
29.11 Register Summary - Timer2
30 UTMR - Universal Timer Module
30.1 Module Nomenclature
30.2 Clock Source Selection
30.3 UTMR Prescaler
30.4 UTMR Operation
30.5 UTMR Output Modes
30.6 Interrupt and DMA Triggers
30.7 Operation During Sleep
30.8 Chaining Counter Timers
30.9 Register Definitions: Universal Timer
30.10 Register Summary - Universal Timer
31 CCP - Capture/Compare/PWM Module
31.1 CCP Module Configuration
31.2 Capture Mode
31.3 Compare Mode
31.4 PWM Overview
31.5 Register Definitions: CCP Control
31.6 Register Summary - CCP Control
32 Capture, Compare, and PWM Timers Selection
32.1 Register Definitions: Capture, Compare, and PWM Timers Selection
32.2 Register Summary - Capture, Compare, and PWM Timers Selection
33 PWM - Pulse-Width Modulator with Compare
33.1 Output Slices
33.2 Period Timer
33.3 Clock Sources
33.4 External Period Resets
33.5 Buffered Period and Parameter Registers
33.6 Synchronizing Multiple PWMs
33.7 Interrupts
33.8 Operation During Sleep
33.9 Register Definitions: PWM Control
33.10 Register Summary - PWM
34 CWG - Complementary Waveform Generator Module
34.1 Fundamental Operation
34.2 Operating Modes
34.3 Clock Source
34.4 Selectable Input Sources
34.5 Output Control
34.6 Dead-Band Control
34.7 Rising Edge and Reverse Dead Band
34.8 Falling Edge and Forward Dead Band
34.9 Dead-Band Jitter
34.10 Auto-Shutdown
34.11 Auto-Shutdown Restart
34.12 Operation During Sleep
34.13 Configuring the CWG
34.14 Register Definitions: CWG Control
34.15 Register Summary - CWG
35 NCO - Numerically Controlled Oscillator Module
35.1 NCO Operation
35.2 Fixed Duty Cycle Mode
35.3 Pulse Frequency Mode
35.4 Output Polarity Control
35.5 Interrupts
35.6 Effects of a Reset
35.7 Operation in Sleep
35.8 Register Definitions: NCO
35.9 Register Summary - NCO
36 DSM - Data Signal Modulator Module
36.1 DSM Operation
36.2 Carrier Synchronization
36.3 Carrier Source Polarity Select
36.4 Programmable Modulator Data
36.5 Modulated Output Polarity
36.6 Operation in Sleep Mode
36.7 Effects of a Reset
36.8 Peripheral Module Disable
36.9 Register Definitions: Modulation Control
36.10 Register Summary - DSM
37 UART - Universal Asynchronous Receiver Transmitter with Protocol Support
37.1 UART I/O Pin Configuration
37.2 UART Asynchronous Modes
37.3 DMX Mode (Full-Featured UARTs Only)
37.4 LIN Modes (Full-Featured UARTs Only)
37.5 DALI Mode (Full-Featured UARTs Only)
37.6 General Purpose Manchester (Full-Featured UARTs Only)
37.7 Polarity
37.8 Stop Bits
37.9 Operation After FIFO Overflow
37.10 Receive and Transmit Buffers
37.11 Flow Control
37.12 Checksum (Full-Featured UARTs Only)
37.13 Collision Detection (Full-Featured UARTs Only)
37.14 RX/TX Activity Time-Out
37.15 Clock Accuracy with Asynchronous Operation
37.16 UART Baud Rate Generator
37.17 Transmitting a Break
37.18 Receiving a Break
37.19 UART Operation During Sleep
37.20 Register Definitions: UART
37.21 Register Summary - UART
38 SPI - Serial Peripheral Interface Module
38.1 SPI Controls
38.2 SPI Operation
38.3 Host Mode
38.4 Client Mode
38.5 SPI Operation in Sleep Mode
38.6 SPI Interrupts
38.7 Register Definitions: Serial Peripheral Interface
38.8 Register Summary - SPI Control
39 I2C - Inter-Integrated Circuit Module
39.1 I2C Features
39.2 I2C Terminology
39.3 I2C Module Overview
39.4 I2C Operation
39.5 Register Definitions: I2C Control
39.6 Register Summary - I2C
40 HLVD - High/Low-Voltage Detect
40.1 Operation
40.2 Setup
40.3 Current Consumption
40.4 HLVD Start-Up Time
40.5 Applications
40.6 Operation During Sleep
40.7 Operation During Idle and Doze Modes
40.8 Effects of a Reset
40.9 Register Definitions: HLVD Control
40.10 Register Summary - HLVD
41 FVR - Fixed Voltage Reference
41.1 Independent Gain Amplifiers
41.2 FVR Stabilization Period
41.3 Register Definitions: FVR
41.4 Register Summary - FVR
42 Temperature Indicator Module
42.1 Module Operation
42.2 Temperature Calculation
42.3 ADC Acquisition Time
42.4 Register Definitions: Temperature Indicator
42.5 Register Summary - Temperature Indicator
43 ADC - Analog-to-Digital Converter with Computation Module
43.1 ADC Configuration
43.2 ADC Operation
43.3 ADC Acquisition Requirements
43.4 Computation Operation
43.5 Register Definitions: ADC Control
43.6 Register Summary - ADC
44 DAC - Digital-to-Analog Converter Module
44.1 Output Voltage Selection
44.2 Ratiometric Output Level
44.3 Operation During Sleep
44.4 Effects of a Reset
44.5 Register Definitions: DAC Control
44.6 Register Summary - DAC
45 CMP - Comparator Module
45.1 Comparator Overview
45.2 Comparator Control
45.3 Comparator Output Synchronization
45.4 Comparator Hysteresis
45.5 Comparator Interrupt
45.6 Comparator Positive Input Selection
45.7 Comparator Negative Input Selection
45.8 Comparator Response Time
45.9 Analog Input Connection Considerations
45.10 Operation in Sleep Mode
45.11 ADC Auto-Trigger Source
45.12 Register Definitions: Comparator Control
45.13 Register Summary - Comparator
46 ZCD - Zero-Cross Detection Module
46.1 External Resistor Selection
46.2 ZCD Logic Output
46.3 ZCD Logic Polarity
46.4 ZCD Interrupts
46.5 Correction for ZCPINV Offset
46.6 Handling VPEAK Variations
46.7 Operation During Sleep
46.8 Effects of a Reset
46.9 Disabling the ZCD Module
46.10 Register Definitions: ZCD Control
46.11 Register Summary - ZCD
47 Instruction Set Summary
47.1 Standard Instruction Set
47.2 Extended Instruction Set
48 ICSP™ - In-Circuit Serial Programming™
48.1 High-Voltage Programming Entry Mode
48.2 Low-Voltage Programming Entry Mode
48.3 Common Programming Interfaces
49 Register Summary
50 Electrical Specifications
50.1 Absolute Maximum Ratings
50.2 Standard Operating Conditions
50.3 DC Characteristics
50.4 AC Characteristics
51 DC and AC Characteristics Graphs and Tables
52 Packaging Information
52.1 Package Details
53 Appendix A: Revision History
Product Identification System
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature

DS40002671A

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