Write Combining Buffer (WCB)

WCB combines multiple consecutive writes to a given address range into a TileLink burst to increase the efficiency of Write transactions. Read Transactions are bypassed by WCB. WCB accesses the 256 MB of non-cached DDR region via system port 4 AXI-NC as shown in the following table.

Table 1. WCB Address Range
WCB Address Range
Base Address	Top	Port
0xD000_0000	0xDFFF_FFFF	System Port 4 (AXI4-NC)
0x18_0000_0000	0x1B_FFFF_FFFF	System Port 4 (AXI4-NC)

WCB manages its internal buffers efficiently based on the incoming Write/Read transaction addresses. The key properties of WCB are as follows:

The WCB supports all single byte, multi-byte, and word writes (any single beat writes).
Multi-beat transactions bypass WCB
If all internal buffers are in use, and a write to a different base address occurs, the WCB may insert idle cycles while it empties a buffer.
A buffer in WCB is also emptied under the following conditions:
- All bytes in the buffer have been written.
- The buffer is not written for idle cycles.
- A write to WCB address range followed by a read of the same address will cause a buffer to flush. The read is not allowed to pass through the WCB until the write has completed.
- A write from a different master that matches a buffer’s base address.
- A write from the same master to an already written byte(s) in the buffer.